JPS5665553A - Data communication control system - Google Patents

Data communication control system

Info

Publication number
JPS5665553A
JPS5665553A JP14091279A JP14091279A JPS5665553A JP S5665553 A JPS5665553 A JP S5665553A JP 14091279 A JP14091279 A JP 14091279A JP 14091279 A JP14091279 A JP 14091279A JP S5665553 A JPS5665553 A JP S5665553A
Authority
JP
Japan
Prior art keywords
input
data
response data
circuit
inquiry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14091279A
Other languages
Japanese (ja)
Other versions
JPS6356739B2 (en
Inventor
Nobumasa Mori
Keizo Mizuguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14091279A priority Critical patent/JPS5665553A/en
Publication of JPS5665553A publication Critical patent/JPS5665553A/en
Publication of JPS6356739B2 publication Critical patent/JPS6356739B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Computer And Data Communications (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To increase the usage efficiency of memory device while preventing the production of clinch state, by storing the inquiry data and the response data to common memory device and making different the input regulated value of both the input data. CONSTITUTION:The inquiry data input from an inquiry data input circuit 15 and the response data input from a response data input circuit 13 are all stored in a buffer memory device 11 in common use for waiting control. Further, the data are delivered to a central processing unit CPU via an inquiry data output circuit 12 and to a terminal IO side via a response data output circuit 14. In this case, the state of usage of memory unit is monitored at a monitor 16, and if the rate of usage is increased, the input limit of inquiry data is made with a response data input limit circuit 19. Further, if the rate is decreased, the input limit is released in the way of inversion, with respective limit release circuits 18 and 20.
JP14091279A 1979-10-31 1979-10-31 Data communication control system Granted JPS5665553A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14091279A JPS5665553A (en) 1979-10-31 1979-10-31 Data communication control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14091279A JPS5665553A (en) 1979-10-31 1979-10-31 Data communication control system

Publications (2)

Publication Number Publication Date
JPS5665553A true JPS5665553A (en) 1981-06-03
JPS6356739B2 JPS6356739B2 (en) 1988-11-09

Family

ID=15279702

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14091279A Granted JPS5665553A (en) 1979-10-31 1979-10-31 Data communication control system

Country Status (1)

Country Link
JP (1) JPS5665553A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0295046A (en) * 1988-09-30 1990-04-05 Nippon Telegr & Teleph Corp <Ntt> Information repeating closing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0295046A (en) * 1988-09-30 1990-04-05 Nippon Telegr & Teleph Corp <Ntt> Information repeating closing system

Also Published As

Publication number Publication date
JPS6356739B2 (en) 1988-11-09

Similar Documents

Publication Publication Date Title
JPS5665553A (en) Data communication control system
JPS5429534A (en) Adding system of optional functions to composite terminal
JPS55108057A (en) Duplex control unit
JPS54156433A (en) Buffer memory control system
JPS57208689A (en) Memory control device
JPS5587220A (en) Interface controller
JPS5338236A (en) Multi-computer system
JPS5493340A (en) Duplex processing system
JPS51113431A (en) Coupling control system between input-output buses
JPS5733472A (en) Memory access control system
JPS54121630A (en) Inter-unit interface system
JPS57174723A (en) Bus load controlling system
JPS5697124A (en) Connection disconnection system for terminal device
JPS564826A (en) Electronic computer
JPS5616221A (en) Control system for data transfer
JPS6478353A (en) Data transfer method for microcomputer
JPS5373934A (en) Data exchange control system
JPS57182248A (en) Arithmetic processor
JPS5595450A (en) Timer clocking system of communication controller
JPS5377148A (en) Input and output control circuit
JPS57105032A (en) Queue loading control system of signal processing device
JPS51144137A (en) Input/output data control unit
JPS57101928A (en) Interruption controlling system
JPS6476259A (en) Control system for dual cpu system
JPS54122050A (en) Terminal controller