JPS5665553A - Data communication control system - Google Patents
Data communication control systemInfo
- Publication number
- JPS5665553A JPS5665553A JP14091279A JP14091279A JPS5665553A JP S5665553 A JPS5665553 A JP S5665553A JP 14091279 A JP14091279 A JP 14091279A JP 14091279 A JP14091279 A JP 14091279A JP S5665553 A JPS5665553 A JP S5665553A
- Authority
- JP
- Japan
- Prior art keywords
- input
- data
- response data
- circuit
- inquiry
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
- Computer And Data Communications (AREA)
- Small-Scale Networks (AREA)
- Communication Control (AREA)
Abstract
PURPOSE:To increase the usage efficiency of memory device while preventing the production of clinch state, by storing the inquiry data and the response data to common memory device and making different the input regulated value of both the input data. CONSTITUTION:The inquiry data input from an inquiry data input circuit 15 and the response data input from a response data input circuit 13 are all stored in a buffer memory device 11 in common use for waiting control. Further, the data are delivered to a central processing unit CPU via an inquiry data output circuit 12 and to a terminal IO side via a response data output circuit 14. In this case, the state of usage of memory unit is monitored at a monitor 16, and if the rate of usage is increased, the input limit of inquiry data is made with a response data input limit circuit 19. Further, if the rate is decreased, the input limit is released in the way of inversion, with respective limit release circuits 18 and 20.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14091279A JPS5665553A (en) | 1979-10-31 | 1979-10-31 | Data communication control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14091279A JPS5665553A (en) | 1979-10-31 | 1979-10-31 | Data communication control system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5665553A true JPS5665553A (en) | 1981-06-03 |
JPS6356739B2 JPS6356739B2 (en) | 1988-11-09 |
Family
ID=15279702
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14091279A Granted JPS5665553A (en) | 1979-10-31 | 1979-10-31 | Data communication control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5665553A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0295046A (en) * | 1988-09-30 | 1990-04-05 | Nippon Telegr & Teleph Corp <Ntt> | Information repeating closing system |
-
1979
- 1979-10-31 JP JP14091279A patent/JPS5665553A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0295046A (en) * | 1988-09-30 | 1990-04-05 | Nippon Telegr & Teleph Corp <Ntt> | Information repeating closing system |
Also Published As
Publication number | Publication date |
---|---|
JPS6356739B2 (en) | 1988-11-09 |
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