JPS5665395A - Bit-line voltage level setting circuit - Google Patents
Bit-line voltage level setting circuitInfo
- Publication number
- JPS5665395A JPS5665395A JP14008779A JP14008779A JPS5665395A JP S5665395 A JPS5665395 A JP S5665395A JP 14008779 A JP14008779 A JP 14008779A JP 14008779 A JP14008779 A JP 14008779A JP S5665395 A JPS5665395 A JP S5665395A
- Authority
- JP
- Japan
- Prior art keywords
- bit
- line voltage
- cell
- voltage level
- setting circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/10—SRAM devices comprising bipolar components
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
- G11C11/4113—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
- G11C11/416—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14008779A JPS5665395A (en) | 1979-10-30 | 1979-10-30 | Bit-line voltage level setting circuit |
IE2178/80A IE50694B1 (en) | 1979-10-30 | 1980-10-21 | Semiconductor integrated circuit memory device with integrated injection logic |
US06/200,217 US4373195A (en) | 1979-10-30 | 1980-10-24 | Semiconductor integrated circuit device |
DE8080303830T DE3067375D1 (en) | 1979-10-30 | 1980-10-28 | Semiconductor integrated circuit memory device with integrated injection logic |
EP80303830A EP0028157B1 (en) | 1979-10-30 | 1980-10-28 | Semiconductor integrated circuit memory device with integrated injection logic |
CA000363439A CA1157949A (en) | 1979-10-30 | 1980-10-28 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14008779A JPS5665395A (en) | 1979-10-30 | 1979-10-30 | Bit-line voltage level setting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5665395A true JPS5665395A (en) | 1981-06-03 |
Family
ID=15260645
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14008779A Pending JPS5665395A (en) | 1979-10-30 | 1979-10-30 | Bit-line voltage level setting circuit |
Country Status (6)
Country | Link |
---|---|
US (1) | US4373195A (ja) |
EP (1) | EP0028157B1 (ja) |
JP (1) | JPS5665395A (ja) |
CA (1) | CA1157949A (ja) |
DE (1) | DE3067375D1 (ja) |
IE (1) | IE50694B1 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5789154A (en) | 1980-11-25 | 1982-06-03 | Nec Corp | Logical integrated circuit |
US4388705A (en) * | 1981-10-01 | 1983-06-14 | Mostek Corporation | Semiconductor memory circuit |
DE3227121A1 (de) * | 1982-07-20 | 1984-01-26 | Siemens AG, 1000 Berlin und 8000 München | Schaltungsanordnung zum lesen bipolarer speicherzellen |
US4791613A (en) * | 1983-09-21 | 1988-12-13 | Inmos Corporation | Bit line and column circuitry used in a semiconductor memory |
US4627032A (en) * | 1983-11-25 | 1986-12-02 | At&T Bell Laboratories | Glitch lockout circuit for memory array |
US4813017A (en) * | 1985-10-28 | 1989-03-14 | International Business Machines Corportion | Semiconductor memory device and array |
US4701882A (en) * | 1985-12-16 | 1987-10-20 | Motorola, Inc. | Bipolar RAM cell |
US4697251A (en) * | 1985-12-16 | 1987-09-29 | Motorola, Inc. | Bipolar RAM cell |
JP2516962B2 (ja) * | 1987-03-18 | 1996-07-24 | 三菱電機株式会社 | マスタ−スライスlsi |
CN113517008B (zh) * | 2020-04-10 | 2024-06-11 | 中国科学院微电子研究所 | 一种动态钳位存内计算电路、存储器以及电子设备 |
CN116088631B (zh) * | 2023-04-11 | 2023-06-30 | 长鑫存储技术有限公司 | 一种电源电路和存储器 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4057789A (en) * | 1974-06-19 | 1977-11-08 | International Business Machines Corporation | Reference voltage source for memory cells |
US4075609A (en) * | 1976-04-29 | 1978-02-21 | Motorola, Inc. | On-chip voltage source for integrated circuits |
DE2657561B1 (de) * | 1976-12-18 | 1978-04-13 | Ibm Deutschland | Nachlade-Referenzschaltungsanordnung fuer einen Halbleiterspeicher |
DE2738187C2 (de) * | 1977-08-24 | 1979-02-15 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Schaltungsanordnung für mehrere auf einem Bipolar-Baustein angeordnete Speicherzellen mit einer Regelschaltung zur Kennlinien-Anpassung der Speicherzellen |
US4112511A (en) * | 1977-09-13 | 1978-09-05 | Signetics Corporation | Four transistor static bipolar memory cell using merged transistors |
JPS564263A (en) * | 1979-06-25 | 1981-01-17 | Hitachi Ltd | Semiconductor memory |
-
1979
- 1979-10-30 JP JP14008779A patent/JPS5665395A/ja active Pending
-
1980
- 1980-10-21 IE IE2178/80A patent/IE50694B1/en not_active IP Right Cessation
- 1980-10-24 US US06/200,217 patent/US4373195A/en not_active Expired - Lifetime
- 1980-10-28 DE DE8080303830T patent/DE3067375D1/de not_active Expired
- 1980-10-28 CA CA000363439A patent/CA1157949A/en not_active Expired
- 1980-10-28 EP EP80303830A patent/EP0028157B1/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
IE802178L (en) | 1981-04-30 |
CA1157949A (en) | 1983-11-29 |
IE50694B1 (en) | 1986-06-25 |
US4373195A (en) | 1983-02-08 |
EP0028157A1 (en) | 1981-05-06 |
DE3067375D1 (en) | 1984-05-10 |
EP0028157B1 (en) | 1984-04-04 |
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