JPS5660060A - Mos semiconductor device - Google Patents

Mos semiconductor device

Info

Publication number
JPS5660060A
JPS5660060A JP13516379A JP13516379A JPS5660060A JP S5660060 A JPS5660060 A JP S5660060A JP 13516379 A JP13516379 A JP 13516379A JP 13516379 A JP13516379 A JP 13516379A JP S5660060 A JPS5660060 A JP S5660060A
Authority
JP
Japan
Prior art keywords
impurity density
gate
type
represented
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13516379A
Other languages
Japanese (ja)
Inventor
Kazumichi Sakamoto
Yasuo Taira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13516379A priority Critical patent/JPS5660060A/en
Publication of JPS5660060A publication Critical patent/JPS5660060A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To reduce the parasitic capacity of the MOS semiconductor device by setting each value at C1>C2>C3, where the impurity density under the insulating film of the first gate is represented by C1, the impurity density under the insulating film of the second gate is represented by C2 and the impurity density of a substrate is represented by C3. CONSTITUTION:Boron ions are implanted to a p type Si substrate 1 having for example 5X10<14>/cm<3> of impurity density, and the first gage 6 is thus formed. Subsequently, phosphorus is diffused, and n<+> type regions 3, 4 are formed for contact. A photoresist mask 8 is then formed, boron ions are again implanted, and the first and second gates 6, 9 are formed. Thus, the impurity density of the p<+> type first gate 6 side becomes 1X10<16>/cm<3> and the impurity density of p<+> type second gate 9 side becomes 5X10<15>/cm<3>. Thereafter, molybdenum is formed by spattering, and the first and second gate electrodes G1, G2 are formed.
JP13516379A 1979-10-22 1979-10-22 Mos semiconductor device Pending JPS5660060A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13516379A JPS5660060A (en) 1979-10-22 1979-10-22 Mos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13516379A JPS5660060A (en) 1979-10-22 1979-10-22 Mos semiconductor device

Publications (1)

Publication Number Publication Date
JPS5660060A true JPS5660060A (en) 1981-05-23

Family

ID=15145289

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13516379A Pending JPS5660060A (en) 1979-10-22 1979-10-22 Mos semiconductor device

Country Status (1)

Country Link
JP (1) JPS5660060A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5887875A (en) * 1981-11-20 1983-05-25 Hitachi Ltd Twin-gate type mis semiconductor device
JPH01128569A (en) * 1987-11-13 1989-05-22 Nec Corp Field effect transistor
JPH07227412A (en) * 1993-12-22 1995-08-29 Minoru Sasaki Armpit rest for enabling vertical action

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4936358A (en) * 1972-08-07 1974-04-04
JPS54986A (en) * 1977-06-06 1979-01-06 Hitachi Ltd Reducing method of voltage dependancy for fet output capacity

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4936358A (en) * 1972-08-07 1974-04-04
JPS54986A (en) * 1977-06-06 1979-01-06 Hitachi Ltd Reducing method of voltage dependancy for fet output capacity

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5887875A (en) * 1981-11-20 1983-05-25 Hitachi Ltd Twin-gate type mis semiconductor device
JPH01128569A (en) * 1987-11-13 1989-05-22 Nec Corp Field effect transistor
JPH07227412A (en) * 1993-12-22 1995-08-29 Minoru Sasaki Armpit rest for enabling vertical action

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