JPS5657351A - Serial data reception system - Google Patents

Serial data reception system

Info

Publication number
JPS5657351A
JPS5657351A JP13399879A JP13399879A JPS5657351A JP S5657351 A JPS5657351 A JP S5657351A JP 13399879 A JP13399879 A JP 13399879A JP 13399879 A JP13399879 A JP 13399879A JP S5657351 A JPS5657351 A JP S5657351A
Authority
JP
Japan
Prior art keywords
buffers
data
address
cpu
serial data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13399879A
Other languages
Japanese (ja)
Other versions
JPS6019821B2 (en
Inventor
Kanji Kanai
Haruka Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP13399879A priority Critical patent/JPS6019821B2/en
Priority to DE19803039306 priority patent/DE3039306C2/en
Publication of JPS5657351A publication Critical patent/JPS5657351A/en
Publication of JPS6019821B2 publication Critical patent/JPS6019821B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To ensure a high-efficiency process, by storing the address and data parts into the different reception buffers and then producing the interruption signal to the CPU for the reception of eithr one or both of the address and data parts.
CONSTITUTION: The address buffers AB1∼AB4 and the data buffes DB1∼DB4 are provided to the serial data reception circuit, and the serial data sent from the terminal unit are applied to the gates G1 and G2 each. Then a decision is given between the address and the data by the output given from the address/data deciding FF11 to be stored in the buffers AB4 and DB4 each. Both the address and the data of the buffers AB4 and DB4 are transferred successively to the buffers AB3∼AB1 and the buffers DB3∼DB1. And the interruption signals INT1 and INT2 are sent to the CPU from the buffers AB1 and DB1 each, and the buffer and the data are sent to the CPU from the buffers AB1 and DB1 each.
COPYRIGHT: (C)1981,JPO&Japio
JP13399879A 1979-10-17 1979-10-17 Serial data reception method Expired JPS6019821B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP13399879A JPS6019821B2 (en) 1979-10-17 1979-10-17 Serial data reception method
DE19803039306 DE3039306C2 (en) 1979-10-17 1980-10-17 Device for receiving asynchronous and bit-by-bit serially transmitted data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13399879A JPS6019821B2 (en) 1979-10-17 1979-10-17 Serial data reception method

Publications (2)

Publication Number Publication Date
JPS5657351A true JPS5657351A (en) 1981-05-19
JPS6019821B2 JPS6019821B2 (en) 1985-05-18

Family

ID=15117986

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13399879A Expired JPS6019821B2 (en) 1979-10-17 1979-10-17 Serial data reception method

Country Status (2)

Country Link
JP (1) JPS6019821B2 (en)
DE (1) DE3039306C2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60551A (en) * 1983-06-16 1985-01-05 Hitachi Ltd Central processor of data transmitting system
JPS6361356A (en) * 1986-09-01 1988-03-17 Nec Corp Serial data transfer device
JPS63287139A (en) * 1987-05-19 1988-11-24 Sharp Corp Serial communication system

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4912723A (en) * 1984-06-28 1990-03-27 Westinghouse Electric Corp. Multipurpose digital IC for communication and control network
FR2568035B1 (en) * 1984-07-17 1989-06-02 Sagem METHOD FOR INTERCONNECTING MICROPROCESSORS
DE3624665A1 (en) * 1986-07-22 1988-01-28 Bosch Gmbh Robert Circuit arrangement for switching various electrical loads on and off
FR2773657B1 (en) 1998-01-14 2001-12-28 Sgs Thomson Microelectronics COMMUNICATION METHOD WITH COHERENCE CONTROL AND DEVICE FOR IMPLEMENTING IT

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6046585B2 (en) * 1979-03-06 1985-10-16 株式会社リコー Serial data transmission method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60551A (en) * 1983-06-16 1985-01-05 Hitachi Ltd Central processor of data transmitting system
JPH0312746B2 (en) * 1983-06-16 1991-02-20 Hitachi Ltd
JPS6361356A (en) * 1986-09-01 1988-03-17 Nec Corp Serial data transfer device
JPS63287139A (en) * 1987-05-19 1988-11-24 Sharp Corp Serial communication system
JPH0748732B2 (en) * 1987-05-19 1995-05-24 シャープ株式会社 Serial communication system

Also Published As

Publication number Publication date
JPS6019821B2 (en) 1985-05-18
DE3039306C2 (en) 1986-08-14
DE3039306A1 (en) 1981-05-07

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