JPS5654053A - Formation of multilayer wiring - Google Patents

Formation of multilayer wiring

Info

Publication number
JPS5654053A
JPS5654053A JP13037879A JP13037879A JPS5654053A JP S5654053 A JPS5654053 A JP S5654053A JP 13037879 A JP13037879 A JP 13037879A JP 13037879 A JP13037879 A JP 13037879A JP S5654053 A JPS5654053 A JP S5654053A
Authority
JP
Japan
Prior art keywords
layer
wiring
grown
wiring layer
nitride film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13037879A
Other languages
Japanese (ja)
Inventor
Masahiko Denda
Shinichi Sato
Wataru Wakamiya
Hiroji Harada
Natsuo Tsubouchi
Hirokazu Miyoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13037879A priority Critical patent/JPS5654053A/en
Priority to US06/184,171 priority patent/US4381595A/en
Priority to DE3033513A priority patent/DE3033513C2/en
Publication of JPS5654053A publication Critical patent/JPS5654053A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent the mutual diffusion between the wiring layer made of an Al or Al alloy by imparting the surface of a plasma CVD nitride film an oxidizing property. CONSTITUTION:An opening 3 is made in an oxide film 3 on a semiconductor substrate 1 and an Al wiring layer 4 is made thereon. Then, plasma is generated in a gas mixture of SiH4, MH3 and N2 to have a nitride film 5 grown and then, a gas having an oxidizing property such as O2 is mixed to have an SixOyNy layer 5' grown on the surface layer. Then, a through hole 6 is provided to form an Al wiring layer 7 as in the past. With such an arrangement, there is no short-circuit between the Al wiring layers 4 and 7 despite several hours of sintering at 500 deg.C thereby improving the reliability of the device. the same effect can be obtained when a thin Si-rich layer is made on he surface layer in addition to the oxynitride layer by increasing the mixing ratio of NH3.
JP13037879A 1979-10-09 1979-10-09 Formation of multilayer wiring Pending JPS5654053A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP13037879A JPS5654053A (en) 1979-10-09 1979-10-09 Formation of multilayer wiring
US06/184,171 US4381595A (en) 1979-10-09 1980-09-04 Process for preparing multilayer interconnection
DE3033513A DE3033513C2 (en) 1979-10-09 1980-09-05 Process for the production of an aluminum-containing conductor layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13037879A JPS5654053A (en) 1979-10-09 1979-10-09 Formation of multilayer wiring

Publications (1)

Publication Number Publication Date
JPS5654053A true JPS5654053A (en) 1981-05-13

Family

ID=15032905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13037879A Pending JPS5654053A (en) 1979-10-09 1979-10-09 Formation of multilayer wiring

Country Status (1)

Country Link
JP (1) JPS5654053A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3206421A1 (en) * 1982-02-23 1983-09-01 Siemens AG, 1000 Berlin und 8000 München METHOD FOR PRODUCING LAYERS FROM HIGH-MELTING METALS OR METAL COMPOUNDS THROUGH VAPOR PHASE DEPOSITION

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3206421A1 (en) * 1982-02-23 1983-09-01 Siemens AG, 1000 Berlin und 8000 München METHOD FOR PRODUCING LAYERS FROM HIGH-MELTING METALS OR METAL COMPOUNDS THROUGH VAPOR PHASE DEPOSITION

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