JPS5644178A - Buffer memory control system - Google Patents

Buffer memory control system

Info

Publication number
JPS5644178A
JPS5644178A JP11890979A JP11890979A JPS5644178A JP S5644178 A JPS5644178 A JP S5644178A JP 11890979 A JP11890979 A JP 11890979A JP 11890979 A JP11890979 A JP 11890979A JP S5644178 A JPS5644178 A JP S5644178A
Authority
JP
Japan
Prior art keywords
bits
address
logical
entry
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11890979A
Other languages
Japanese (ja)
Other versions
JPS5821352B2 (en
Inventor
Masao Kato
Tsutomu Sumimoto
Masayuki Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP54118909A priority Critical patent/JPS5821352B2/en
Publication of JPS5644178A publication Critical patent/JPS5644178A/en
Publication of JPS5821352B2 publication Critical patent/JPS5821352B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To shorten the time of access to a buffer memory by carrying out conversion from logical page addresses to actual page addresses and buffer memory access in parallel.
CONSTITUTION: While access to one entry in coordinate table TLB21 is attained by seven bits, bit 13W19, of logical address LA, access to buffer address array 2 is also attained by nine bits 18W26. Since TLB21 contains 128(27) entries that correspond to logical addresses LA, a corresponding entry is found by seven bits 13W19 and while nine bits 4W12 of logical address LA are read out of the entry, the actual page address of bits 8W19(12 bits) of corresponding actual address RA is also read out. Then, identity detecting circuit 26 compares nine bits 4W12 in logical address register 18 to nine bits 4W12 of the logical page address in the TLB entry. When they agree, an actual page address to be found is considered to be in the TLB entry.
COPYRIGHT: (C)1981,JPO&Japio
JP54118909A 1979-09-17 1979-09-17 Buffer memory control method Expired JPS5821352B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54118909A JPS5821352B2 (en) 1979-09-17 1979-09-17 Buffer memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54118909A JPS5821352B2 (en) 1979-09-17 1979-09-17 Buffer memory control method

Publications (2)

Publication Number Publication Date
JPS5644178A true JPS5644178A (en) 1981-04-23
JPS5821352B2 JPS5821352B2 (en) 1983-04-28

Family

ID=14748163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54118909A Expired JPS5821352B2 (en) 1979-09-17 1979-09-17 Buffer memory control method

Country Status (1)

Country Link
JP (1) JPS5821352B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5864689A (en) * 1981-10-14 1983-04-18 Hitachi Ltd Data processor
JPS58150186A (en) * 1982-03-03 1983-09-06 Nec Corp System for controlling buffer memory
JPS60221851A (en) * 1984-02-17 1985-11-06 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Data processor and memory access controller used therefor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51124334A (en) * 1975-04-23 1976-10-29 Toshiba Corp Information processing unit
JPS52149924A (en) * 1976-06-09 1977-12-13 Hitachi Ltd Address converter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51124334A (en) * 1975-04-23 1976-10-29 Toshiba Corp Information processing unit
JPS52149924A (en) * 1976-06-09 1977-12-13 Hitachi Ltd Address converter

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5864689A (en) * 1981-10-14 1983-04-18 Hitachi Ltd Data processor
JPH056706B2 (en) * 1981-10-14 1993-01-27 Hitachi Seisakusho Kk
JPS58150186A (en) * 1982-03-03 1983-09-06 Nec Corp System for controlling buffer memory
JPS6213699B2 (en) * 1982-03-03 1987-03-28 Nippon Electric Co
JPS60221851A (en) * 1984-02-17 1985-11-06 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Data processor and memory access controller used therefor
JPH0531776B2 (en) * 1984-02-17 1993-05-13 Fuiritsupusu Furuuiranpenfuaburiken Nv

Also Published As

Publication number Publication date
JPS5821352B2 (en) 1983-04-28

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