JPS5623758A - Semiconductor device and manufacture threof - Google Patents

Semiconductor device and manufacture threof

Info

Publication number
JPS5623758A
JPS5623758A JP9726279A JP9726279A JPS5623758A JP S5623758 A JPS5623758 A JP S5623758A JP 9726279 A JP9726279 A JP 9726279A JP 9726279 A JP9726279 A JP 9726279A JP S5623758 A JPS5623758 A JP S5623758A
Authority
JP
Japan
Prior art keywords
layer
resin
grease
decrease
external appearance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9726279A
Other languages
Japanese (ja)
Inventor
Shinji Ogawa
Hajime Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Hitachi Iruma Electronic Co Ltd
Original Assignee
Hitachi Ltd
Hitachi Tohbu Semiconductor Ltd
Hitachi Iruma Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Tohbu Semiconductor Ltd, Hitachi Iruma Electronic Co Ltd filed Critical Hitachi Ltd
Priority to JP9726279A priority Critical patent/JPS5623758A/en
Publication of JPS5623758A publication Critical patent/JPS5623758A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent improper external appearance of a semiconductor and the decrease of the reliability thereof by employing resin flowing control member layer such as Si grease or Si oil and using surface tension of resin to form smoothly the ends of organic resin layer. CONSTITUTION:Si grease layer 17 is coated to surround a chip 14 in space from the surface of a substrate 11 connected with wires 15. Then, epoxy resin is dropped on the inside of the layer 17. The resin is controlled to expand by the layer 17, is retained in its shape by the surface tension, is heat treated in this state, and is hardended as a coating 16. Then, the grease layer 17 is removed by trichloroethylene. This configuration does not require component for stopping resin, but provides thin and small size. The layer 17 is formed at the ends in smooth shape difficult from damage to reduce improper external appearance and to prevent the decrease of the reliability owing to the reduction of the airtightness of the sealing.
JP9726279A 1979-08-01 1979-08-01 Semiconductor device and manufacture threof Pending JPS5623758A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9726279A JPS5623758A (en) 1979-08-01 1979-08-01 Semiconductor device and manufacture threof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9726279A JPS5623758A (en) 1979-08-01 1979-08-01 Semiconductor device and manufacture threof

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP11464386A Division JPS61292328A (en) 1986-05-21 1986-05-21 Manufacture of semiconductor sealing structure

Publications (1)

Publication Number Publication Date
JPS5623758A true JPS5623758A (en) 1981-03-06

Family

ID=14187619

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9726279A Pending JPS5623758A (en) 1979-08-01 1979-08-01 Semiconductor device and manufacture threof

Country Status (1)

Country Link
JP (1) JPS5623758A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01107562A (en) * 1987-10-20 1989-04-25 Cmk Corp Printed wiring board
JPH01107563A (en) * 1987-10-20 1989-04-25 Cmk Corp Mounting method for chip component on printed wiring board
JPH01107561A (en) * 1987-10-20 1989-04-25 Cmk Corp Printed wiring board
US8191900B2 (en) 2006-02-21 2012-06-05 Toyota Jidosha Kabushiki Kaisha Oil seal

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4837411U (en) * 1971-09-07 1973-05-08

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4837411U (en) * 1971-09-07 1973-05-08

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01107562A (en) * 1987-10-20 1989-04-25 Cmk Corp Printed wiring board
JPH01107563A (en) * 1987-10-20 1989-04-25 Cmk Corp Mounting method for chip component on printed wiring board
JPH01107561A (en) * 1987-10-20 1989-04-25 Cmk Corp Printed wiring board
US8191900B2 (en) 2006-02-21 2012-06-05 Toyota Jidosha Kabushiki Kaisha Oil seal

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