JPS5623010A - Gain limit amplifying circuit - Google Patents

Gain limit amplifying circuit

Info

Publication number
JPS5623010A
JPS5623010A JP9806279A JP9806279A JPS5623010A JP S5623010 A JPS5623010 A JP S5623010A JP 9806279 A JP9806279 A JP 9806279A JP 9806279 A JP9806279 A JP 9806279A JP S5623010 A JPS5623010 A JP S5623010A
Authority
JP
Japan
Prior art keywords
circuit
output
peak hold
amplifying circuit
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9806279A
Other languages
Japanese (ja)
Inventor
Tetsuo Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP9806279A priority Critical patent/JPS5623010A/en
Publication of JPS5623010A publication Critical patent/JPS5623010A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3005—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To decrease the limit recovery time of the gain limit amplifying circuit without distortion of output signal, by providing two peak hold circuits having different time constants. CONSTITUTION:The signal input from the input terminal 21 is output to the output terminal 24 via the voltage control type variable attenuation circuit 22 and the voltage amplifying circuit 23. The output is rectified forward with the full wave rectifying circuit 25 and branched into two peak hold circuits 27, 28 with the buffer amplifying circuit 26. The variable attenuation circuit 22 is controlled with the output of the 1st peak hold circuit 27. The bias voltage at the bias terminal 32 is set so that it is greater than the output voltage of the 1st peak hold circuit 27 including the amplitude of the 2nd peak hold circuit 28 including the amplitude of the drift of the 2nd peak hold circuit 28 at the minimum frequency within the frequency range of input signal and at the limit of gain at the maximum level. Thus, the distortion of signal waveform due to the drift of the output of the circuit 27 can be produced.
JP9806279A 1979-08-02 1979-08-02 Gain limit amplifying circuit Pending JPS5623010A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9806279A JPS5623010A (en) 1979-08-02 1979-08-02 Gain limit amplifying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9806279A JPS5623010A (en) 1979-08-02 1979-08-02 Gain limit amplifying circuit

Publications (1)

Publication Number Publication Date
JPS5623010A true JPS5623010A (en) 1981-03-04

Family

ID=14209832

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9806279A Pending JPS5623010A (en) 1979-08-02 1979-08-02 Gain limit amplifying circuit

Country Status (1)

Country Link
JP (1) JPS5623010A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07897B1 (en) * 1988-12-16 1995-01-11
EP3815233A4 (en) * 2018-06-28 2022-02-23 Texas Instruments Incorporated Peak detection methods, apparatus, and circuits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07897B1 (en) * 1988-12-16 1995-01-11
EP3815233A4 (en) * 2018-06-28 2022-02-23 Texas Instruments Incorporated Peak detection methods, apparatus, and circuits

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