JPS5621361A - Manufacture of dynamic memory cell - Google Patents

Manufacture of dynamic memory cell

Info

Publication number
JPS5621361A
JPS5621361A JP9765479A JP9765479A JPS5621361A JP S5621361 A JPS5621361 A JP S5621361A JP 9765479 A JP9765479 A JP 9765479A JP 9765479 A JP9765479 A JP 9765479A JP S5621361 A JPS5621361 A JP S5621361A
Authority
JP
Japan
Prior art keywords
layer
capacity
substrate
poly
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9765479A
Other languages
Japanese (ja)
Other versions
JPS6138867B2 (en
Inventor
Motoo Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9765479A priority Critical patent/JPS5621361A/en
Publication of JPS5621361A publication Critical patent/JPS5621361A/en
Publication of JPS6138867B2 publication Critical patent/JPS6138867B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Drying Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To prevent the deterioration of transistor characteristics such as a threshold by preventing the formation of a barrier by a capacity P-N junction at the transistor gate region section of the memory cell of 1 transistor 1 capacity. CONSTITUTION:A field oxide film and an oxide thin film 7 for capacity are provided on a P-type Si substrate 5. A B additive poly Si 8 is stacked on the films and high temperature treatment is done in O2 to cover them with an SiO2 film 9. An N<+> layer 11 is made by applying resist masks 10 and by ion implantation. Next, the temperature of the substrate 5 is held at about 200 deg.C and the substrate 5 is exposed to an HF of several Torr. And selective etching removal is applied to the SiO2 9 only under the resist masks. The masks 10 are removed and photo etching is applied to the poly Si by consisting the SiO2 film 9 as a mask. The etching removal is applied to the side face B of the poly Si layer 8 for capacity electrode up to the position slightly behind the edge of the N<+> layer 11. Next, high temperature treatment is applied in H2 and the B is diffused from the poly Si 8 to make a P<+> layer 12 on the substrate 5. In this composition, the area of capacity electrode is smaller than the N<+> layer 11. Therefore, for the gate 13 of a MOSFET, the P<+> layer 12 will be formed without passing over the N<+> layer 11. So a barrier will not be formed and the characteristics of a memory cell will be improved.
JP9765479A 1979-07-31 1979-07-31 Manufacture of dynamic memory cell Granted JPS5621361A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9765479A JPS5621361A (en) 1979-07-31 1979-07-31 Manufacture of dynamic memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9765479A JPS5621361A (en) 1979-07-31 1979-07-31 Manufacture of dynamic memory cell

Publications (2)

Publication Number Publication Date
JPS5621361A true JPS5621361A (en) 1981-02-27
JPS6138867B2 JPS6138867B2 (en) 1986-09-01

Family

ID=14198061

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9765479A Granted JPS5621361A (en) 1979-07-31 1979-07-31 Manufacture of dynamic memory cell

Country Status (1)

Country Link
JP (1) JPS5621361A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5843569A (en) * 1981-09-09 1983-03-14 Nec Corp Manufacture of semiconductor device
JPH01194346A (en) * 1988-01-28 1989-08-04 Toshiba Corp Semiconductor memory device
JPH08317720A (en) * 1996-06-17 1996-12-03 Kubota Corp Combine harvester

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5843569A (en) * 1981-09-09 1983-03-14 Nec Corp Manufacture of semiconductor device
JPH01194346A (en) * 1988-01-28 1989-08-04 Toshiba Corp Semiconductor memory device
JPH08317720A (en) * 1996-06-17 1996-12-03 Kubota Corp Combine harvester
JP2601647B2 (en) * 1996-06-17 1997-04-16 株式会社クボタ Combine

Also Published As

Publication number Publication date
JPS6138867B2 (en) 1986-09-01

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