JPS5617075A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5617075A
JPS5617075A JP9359579A JP9359579A JPS5617075A JP S5617075 A JPS5617075 A JP S5617075A JP 9359579 A JP9359579 A JP 9359579A JP 9359579 A JP9359579 A JP 9359579A JP S5617075 A JPS5617075 A JP S5617075A
Authority
JP
Japan
Prior art keywords
fet
monitor
region
type
diffused
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9359579A
Other languages
Japanese (ja)
Other versions
JPS6217390B2 (en
Inventor
Goro Mitarai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9359579A priority Critical patent/JPS5617075A/en
Publication of JPS5617075A publication Critical patent/JPS5617075A/en
Publication of JPS6217390B2 publication Critical patent/JPS6217390B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To accurately estimate the characteristics of the semiconductor device by equalizing the diffusing depth of gate regions and the impurity density distribution thereof when forming a J-FET body and a monitor J-FET for measuring the saturated current of the channel thereof on the same semiconductor substrate. CONSTITUTION:A J-FET body 1 and a monitor J-FET2 are formed in a P<+>-type semiconductor substrate 7, and the drain saturated current of the FET of the body is estimated by the measured value of the punch-through voltage of the monitor FET. In order to do it, an N-type layer is first epitaxially grown on the substrate 7, is isolated via the P<+>-type region, and the channel region 5 of the body 1 is formed and the channel region 6 of the monitor 2 is formed on the epitaxial layer. Thereafter, a plurality of P<+>-type gate regions 3 are diffused in the region 5, and a plurality of P<+>-type gate regions 4 are diffused in the region 6. At this time the diffusing depth of the regions 3 and 4 are equalized, and the impurity density distributions thereof are also equalized, and an interval between the diffused openings 8' and 9' are defined as within double of the diffusing depth.
JP9359579A 1979-07-20 1979-07-20 Semiconductor device Granted JPS5617075A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9359579A JPS5617075A (en) 1979-07-20 1979-07-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9359579A JPS5617075A (en) 1979-07-20 1979-07-20 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5617075A true JPS5617075A (en) 1981-02-18
JPS6217390B2 JPS6217390B2 (en) 1987-04-17

Family

ID=14086653

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9359579A Granted JPS5617075A (en) 1979-07-20 1979-07-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5617075A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5140775A (en) * 1974-07-26 1976-04-05 Thomson Csf

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5140775A (en) * 1974-07-26 1976-04-05 Thomson Csf

Also Published As

Publication number Publication date
JPS6217390B2 (en) 1987-04-17

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