JPS56167351A - Manufacture of integrated circuit - Google Patents
Manufacture of integrated circuitInfo
- Publication number
- JPS56167351A JPS56167351A JP7036780A JP7036780A JPS56167351A JP S56167351 A JPS56167351 A JP S56167351A JP 7036780 A JP7036780 A JP 7036780A JP 7036780 A JP7036780 A JP 7036780A JP S56167351 A JPS56167351 A JP S56167351A
- Authority
- JP
- Japan
- Prior art keywords
- chips
- bump
- wafer
- resin film
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/79—Apparatus for Tape Automated Bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
- Wire Bonding (AREA)
Abstract
PURPOSE:To obtain the integrated circuit of low production cost, thin type and high reliability by a method wherein a dicing is performed on the IC wafer whereon a bumps was formed, a resin film is coated and after the resin film on the bump was removed, the IC wafer is divided into chips and are mounted on a substrate. CONSTITUTION:The IC wafer 3, consisting of Al whereon an Au bump 32 was formed, is fixed on a nest plate 1 using wax 2. Then, the wafer 3 is cut into chips 31 by a dicing saw and, under this state of condition, resin film 4 is spin coated for example on the whole surface of the chips. Then, the resin film 4 on the bump 32 is removed by performing exposure, developing and the like and after the chips 31 have been removed from the plate 1, the bump on the chips 31 is joined and mounted to the copper foil pattern on a flexible substrate. Through these procedures, the resin sealing process is simplified and a reliable integrated circuit of thin type can be obtained at low cost.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7036780A JPS56167351A (en) | 1980-05-27 | 1980-05-27 | Manufacture of integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7036780A JPS56167351A (en) | 1980-05-27 | 1980-05-27 | Manufacture of integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56167351A true JPS56167351A (en) | 1981-12-23 |
Family
ID=13429391
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7036780A Pending JPS56167351A (en) | 1980-05-27 | 1980-05-27 | Manufacture of integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56167351A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4904610A (en) * | 1988-01-27 | 1990-02-27 | General Instrument Corporation | Wafer level process for fabricating passivated semiconductor devices |
US5243356A (en) * | 1988-08-05 | 1993-09-07 | Seiko Epson Corporation | Antenna circuit and wrist radio instrument |
EP0789394A2 (en) * | 1996-02-07 | 1997-08-13 | Deutsche ITT Industries GmbH | Process for the separation of electronic devices from a body |
KR19980039678A (en) * | 1996-11-28 | 1998-08-17 | 황인길 | How to Form Flip Chip Bumps |
US6680241B2 (en) * | 2000-07-25 | 2004-01-20 | Fujitsu Limited | Method of manufacturing semiconductor devices by dividing wafer into chips and such semiconductor devices |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS515752A (en) * | 1974-07-03 | 1976-01-17 | Hitachi Ltd |
-
1980
- 1980-05-27 JP JP7036780A patent/JPS56167351A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS515752A (en) * | 1974-07-03 | 1976-01-17 | Hitachi Ltd |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4904610A (en) * | 1988-01-27 | 1990-02-27 | General Instrument Corporation | Wafer level process for fabricating passivated semiconductor devices |
US5243356A (en) * | 1988-08-05 | 1993-09-07 | Seiko Epson Corporation | Antenna circuit and wrist radio instrument |
EP0789394A2 (en) * | 1996-02-07 | 1997-08-13 | Deutsche ITT Industries GmbH | Process for the separation of electronic devices from a body |
EP0789394A3 (en) * | 1996-02-07 | 1998-04-29 | Micronas Intermetall GmbH | Process for the separation of electronic devices from a body |
KR19980039678A (en) * | 1996-11-28 | 1998-08-17 | 황인길 | How to Form Flip Chip Bumps |
US6680241B2 (en) * | 2000-07-25 | 2004-01-20 | Fujitsu Limited | Method of manufacturing semiconductor devices by dividing wafer into chips and such semiconductor devices |
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