JPS5616257A - Disc cash control system - Google Patents

Disc cash control system

Info

Publication number
JPS5616257A
JPS5616257A JP9091579A JP9091579A JPS5616257A JP S5616257 A JPS5616257 A JP S5616257A JP 9091579 A JP9091579 A JP 9091579A JP 9091579 A JP9091579 A JP 9091579A JP S5616257 A JPS5616257 A JP S5616257A
Authority
JP
Japan
Prior art keywords
circuit
signal
track
data
cash
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9091579A
Other languages
Japanese (ja)
Inventor
Yuji Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9091579A priority Critical patent/JPS5616257A/en
Publication of JPS5616257A publication Critical patent/JPS5616257A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To increase the system efficiency, by storing all the data content of track immediately to the address of cash area, transferring the required data stored in the track to the main memory area, and reducing the time occupied by the channel for transfer.
CONSTITUTION: When the request instruction of data is made from CPU3 of the information processor main body 2 to the cash control circuit 8, the circuit 8 immediately outputs the attention signal DAS and it is fed to the transfer control circuit 9 via the OR circuit 11. On the other hand, the data are sequentially read out together with the elapse of time at the magnetic disc 5, and the signal AS read out is input to the circuit 9. Further, the circuit 9 reads in the recorded value at the track location of the desired data based on the signal AS immediately after the reception of the signal DAS, and outputs the start signal STR to the serialparallel converter 12. Further, the record is sequentially fed to the transfer buffer 10 to store one track's share to the empty address of the disc cash 6, and the record is transferred to the main memory unit 4 with the control signal.
COPYRIGHT: (C)1981,JPO&Japio
JP9091579A 1979-07-19 1979-07-19 Disc cash control system Pending JPS5616257A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9091579A JPS5616257A (en) 1979-07-19 1979-07-19 Disc cash control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9091579A JPS5616257A (en) 1979-07-19 1979-07-19 Disc cash control system

Publications (1)

Publication Number Publication Date
JPS5616257A true JPS5616257A (en) 1981-02-17

Family

ID=14011707

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9091579A Pending JPS5616257A (en) 1979-07-19 1979-07-19 Disc cash control system

Country Status (1)

Country Link
JP (1) JPS5616257A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58155464A (en) * 1981-11-27 1983-09-16 ストレ−ジ・テクノロジ−・コ−ポレ−シヨン Detection of sequential data stream
JPS60122440A (en) * 1983-12-07 1985-06-29 Hitachi Ltd Information retrieval control system
JPH01269142A (en) * 1988-04-20 1989-10-26 Hitachi Ltd Buffer memory control system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58155464A (en) * 1981-11-27 1983-09-16 ストレ−ジ・テクノロジ−・コ−ポレ−シヨン Detection of sequential data stream
JPS60122440A (en) * 1983-12-07 1985-06-29 Hitachi Ltd Information retrieval control system
JPH01269142A (en) * 1988-04-20 1989-10-26 Hitachi Ltd Buffer memory control system

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