JPS56162138A - Terminal control device - Google Patents

Terminal control device

Info

Publication number
JPS56162138A
JPS56162138A JP6540780A JP6540780A JPS56162138A JP S56162138 A JPS56162138 A JP S56162138A JP 6540780 A JP6540780 A JP 6540780A JP 6540780 A JP6540780 A JP 6540780A JP S56162138 A JPS56162138 A JP S56162138A
Authority
JP
Japan
Prior art keywords
data
register
buffer
terminal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6540780A
Other languages
Japanese (ja)
Other versions
JPS5948418B2 (en
Inventor
Hisashi Tanaka
Kazuichi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55065407A priority Critical patent/JPS5948418B2/en
Publication of JPS56162138A publication Critical patent/JPS56162138A/en
Publication of JPS5948418B2 publication Critical patent/JPS5948418B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To execute a terminal control with flexibility, by discriminating a terminal equipment by a data from the terminal equipment, referring to the contents of a register for registering the information assigned for each terminal, and assigning a necessary capacity to a transmission and receiving buffer. CONSTITUTION:In case when a data is transmitted to a terminal control device 1 from a terminal equipment 7, a discrimination code of a register 4 is fetched to a data transmitting circuit 5, is added to a transmission data and is transmitted. An assigning circuit 8 of the device 1 refers to the assignment information to each terminal in a register 9, and searches a discrimination code which has been added to a receiving data. When a discrimination code of the device 1 is stored already in the register 9, assignment of a transmission and receiving buffer 10 is finished already, therefore, the circuit 8 stores a receiving data in the area assigned by the buffer 10. In case when a discrimination code of the device 1 is not stored yet in the register 9, the circuit 8 stores a receiving data in the assigned area after assigning a necessary capacity to the buffer 10. In this way, the buffer 10 executes an optimum assignment automatically for plural terminals which are different in the quantity of data.
JP55065407A 1980-05-19 1980-05-19 terminal control device Expired JPS5948418B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55065407A JPS5948418B2 (en) 1980-05-19 1980-05-19 terminal control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55065407A JPS5948418B2 (en) 1980-05-19 1980-05-19 terminal control device

Publications (2)

Publication Number Publication Date
JPS56162138A true JPS56162138A (en) 1981-12-12
JPS5948418B2 JPS5948418B2 (en) 1984-11-26

Family

ID=13286135

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55065407A Expired JPS5948418B2 (en) 1980-05-19 1980-05-19 terminal control device

Country Status (1)

Country Link
JP (1) JPS5948418B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58222372A (en) * 1982-06-18 1983-12-24 Sharp Corp Cash register
JPS59119232U (en) * 1983-01-31 1984-08-11 東芝テック株式会社 Cooking machine switch device
JPS62212754A (en) * 1986-03-13 1987-09-18 Fujitsu Ltd Transfer control system for transmission and reception data
JPH01114980A (en) * 1987-10-29 1989-05-08 Oki Electric Ind Co Ltd Cash processor control system for teller's machine
JPH01258048A (en) * 1988-04-06 1989-10-16 Fujitsu Ltd Data transfer circuit
JPH02272661A (en) * 1989-04-14 1990-11-07 Toshiba Corp Area allocating device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58222372A (en) * 1982-06-18 1983-12-24 Sharp Corp Cash register
JPH049351B2 (en) * 1982-06-18 1992-02-19
JPS59119232U (en) * 1983-01-31 1984-08-11 東芝テック株式会社 Cooking machine switch device
JPS62212754A (en) * 1986-03-13 1987-09-18 Fujitsu Ltd Transfer control system for transmission and reception data
JPH0467664B2 (en) * 1986-03-13 1992-10-29 Fujitsu Ltd
JPH01114980A (en) * 1987-10-29 1989-05-08 Oki Electric Ind Co Ltd Cash processor control system for teller's machine
JPH01258048A (en) * 1988-04-06 1989-10-16 Fujitsu Ltd Data transfer circuit
JPH02272661A (en) * 1989-04-14 1990-11-07 Toshiba Corp Area allocating device

Also Published As

Publication number Publication date
JPS5948418B2 (en) 1984-11-26

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