JPS56138347A - Elastic memory controlling circuit - Google Patents

Elastic memory controlling circuit

Info

Publication number
JPS56138347A
JPS56138347A JP4178980A JP4178980A JPS56138347A JP S56138347 A JPS56138347 A JP S56138347A JP 4178980 A JP4178980 A JP 4178980A JP 4178980 A JP4178980 A JP 4178980A JP S56138347 A JPS56138347 A JP S56138347A
Authority
JP
Japan
Prior art keywords
circuit
signal
clock
reset
elastic memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4178980A
Other languages
Japanese (ja)
Inventor
Shikitoshi Doumori
Yoshibumi Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4178980A priority Critical patent/JPS56138347A/en
Publication of JPS56138347A publication Critical patent/JPS56138347A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To form the alarm signal by using the output of the set/reset flip-flop circuit, by providing the clock interruption detecting circuit detecting the clock interruption from the reception signal and clock signal, and set/reset flip-flop circuit. CONSTITUTION:The reception transmitting line signal (e) having the level converted at the interface circuit 11 is applied to the timing circuit 12, synchronizing circuit 13 and elastic memory circuit 14. When the clock interruption detection circuit 15 detects clock interruption in the clock (f) made at the timing circuit 12, it transmits the signal (g) to one input of the set/reset (S-R) flip-flop circuit 16 as the set signal. On the other hand, the synchronizing circuit 13 feeds the signal (h) to another input of the S-R FF circuit 16 at the synchronizing probability point of the synchronization discriminating pulse as the reset signal. FF16 converts the output signal (j) of the elastic memory circuit into the alarm signal (AIS) with the FF output signal (i).
JP4178980A 1980-03-31 1980-03-31 Elastic memory controlling circuit Pending JPS56138347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4178980A JPS56138347A (en) 1980-03-31 1980-03-31 Elastic memory controlling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4178980A JPS56138347A (en) 1980-03-31 1980-03-31 Elastic memory controlling circuit

Publications (1)

Publication Number Publication Date
JPS56138347A true JPS56138347A (en) 1981-10-28

Family

ID=12618104

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4178980A Pending JPS56138347A (en) 1980-03-31 1980-03-31 Elastic memory controlling circuit

Country Status (1)

Country Link
JP (1) JPS56138347A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01288130A (en) * 1988-05-16 1989-11-20 Matsushita Electric Ind Co Ltd Data expansion circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01288130A (en) * 1988-05-16 1989-11-20 Matsushita Electric Ind Co Ltd Data expansion circuit

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