JPS56137433A - Diagnostic processing system for communication controller - Google Patents

Diagnostic processing system for communication controller

Info

Publication number
JPS56137433A
JPS56137433A JP3926580A JP3926580A JPS56137433A JP S56137433 A JPS56137433 A JP S56137433A JP 3926580 A JP3926580 A JP 3926580A JP 3926580 A JP3926580 A JP 3926580A JP S56137433 A JPS56137433 A JP S56137433A
Authority
JP
Japan
Prior art keywords
data
line
memory
diagnostic
received
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3926580A
Other languages
Japanese (ja)
Other versions
JPS5949611B2 (en
Inventor
Kiyoshi Sato
Masahito Hihara
Tatsuo Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55039265A priority Critical patent/JPS5949611B2/en
Publication of JPS56137433A publication Critical patent/JPS56137433A/en
Publication of JPS5949611B2 publication Critical patent/JPS5949611B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Computer And Data Communications (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To reduce the load for host processor, by supplying the data on the main memory to the 1st line and making folding test so that diagnosis can be made by using the data to the 2nd line. CONSTITUTION:The diagnostic mode in the control information 10 designated with the address M of the diagnostic command DIAG is set with the host processor 1. The folding test data is used by X-byte starting from the address N on the main memory 2. The communication controller 3 receives the control word 8 with the memory 4-1 according to the line A1, and the diagnostic instruction of the control word 9 is received at the memory 4-2 corresponding to the line A2. Further, the device 3 transmits the data for 1 byte's share on the memory 2 to the line 1, the data is received on the line 2, and folded data is received at the memory 4-2. The data is compared with the diagnostic instruction data, and if in uncoincidence, error interruption is made to the device 1. Thus, the amount of data is reduced on the main memory, allowing to reduce the load of the device 1.
JP55039265A 1980-03-27 1980-03-27 Communication control device diagnostic processing method Expired JPS5949611B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55039265A JPS5949611B2 (en) 1980-03-27 1980-03-27 Communication control device diagnostic processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55039265A JPS5949611B2 (en) 1980-03-27 1980-03-27 Communication control device diagnostic processing method

Publications (2)

Publication Number Publication Date
JPS56137433A true JPS56137433A (en) 1981-10-27
JPS5949611B2 JPS5949611B2 (en) 1984-12-04

Family

ID=12548300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55039265A Expired JPS5949611B2 (en) 1980-03-27 1980-03-27 Communication control device diagnostic processing method

Country Status (1)

Country Link
JP (1) JPS5949611B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6366642A (en) * 1986-09-08 1988-03-25 Fanuc Ltd Method for confirming input/output operation
JPH01212142A (en) * 1988-02-19 1989-08-25 Fujitsu Ltd Loopback test system for double loop connecting terminal

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0616213U (en) * 1992-07-31 1994-03-01 鐘紡株式会社 Labeling device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6366642A (en) * 1986-09-08 1988-03-25 Fanuc Ltd Method for confirming input/output operation
JPH01212142A (en) * 1988-02-19 1989-08-25 Fujitsu Ltd Loopback test system for double loop connecting terminal

Also Published As

Publication number Publication date
JPS5949611B2 (en) 1984-12-04

Similar Documents

Publication Publication Date Title
DE2966474D1 (en) Communication controller in a data processing system
JPS56137433A (en) Diagnostic processing system for communication controller
JPS5326632A (en) Common memory control unit
JPS5493305A (en) System operation system in data transmission system
JPS5622157A (en) Process system multiplexing system
JPS5538630A (en) Memory diagnostic system of information processing system
JPS5373934A (en) Data exchange control system
JPS5541511A (en) Micro program control system
JPS56110171A (en) System for designation by responsible person
JPS5547522A (en) Control system of input and output device
JPS575143A (en) Communicating method of multimicroprocessor system
JPS55127790A (en) Duplex system of exchange processing unit
KOCZELA et al. Adaptive voting computer system[Patent]
JPS5734237A (en) Overlapped entry system
JPS575141A (en) Bus control system
JPS54133042A (en) Direct memory access system in multi processor
JPS5682960A (en) Bus control system
JPS6439146A (en) Input/output control lsi with folding function
JPS5696336A (en) Processing system for multilayer level microprogram
JPS57106945A (en) Control system for generation of system operation information
JPS55157059A (en) Microcomputer system
JPS57100679A (en) Buffer memory device
JPS54154235A (en) Data process system containing peripheral unit adaptor
JPS57117054A (en) Data transfer controller of memory
JPS56121160A (en) Common system of common information by main memory level of computer composite equipment