JPS56120247A - Signal detection circuit - Google Patents

Signal detection circuit

Info

Publication number
JPS56120247A
JPS56120247A JP2365680A JP2365680A JPS56120247A JP S56120247 A JPS56120247 A JP S56120247A JP 2365680 A JP2365680 A JP 2365680A JP 2365680 A JP2365680 A JP 2365680A JP S56120247 A JPS56120247 A JP S56120247A
Authority
JP
Japan
Prior art keywords
input
signal
circuit
reception signal
delay circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2365680A
Other languages
Japanese (ja)
Inventor
Takashi Usami
Kensaku Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2365680A priority Critical patent/JPS56120247A/en
Publication of JPS56120247A publication Critical patent/JPS56120247A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
    • H04L25/062—Setting decision thresholds using feedforward techniques only

Abstract

PURPOSE:To save hardware by detecting either one of binary values of reception signal, by sampling the reception signal, and comparing the delayed output with the output of sampling means. CONSTITUTION:The reception signal is sampled and input to an A/D converter 6 from an input terminal 1, where it is converted into a digital signal. The delay time is set at the delay circuit 7 at a shorter time tausec than the signal transmission period. The signal input from the A/D conversion circuit 6 to a comparison circuit 8 is compared with the signal inputted to a delay circuit 7 before tausec. An amplitude comparison circuit 8 outputs 1 when the direct input from the A/D converter 6 is greater than the input from the delay circuit 7, and outputs 0 when smaller.
JP2365680A 1980-02-27 1980-02-27 Signal detection circuit Pending JPS56120247A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2365680A JPS56120247A (en) 1980-02-27 1980-02-27 Signal detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2365680A JPS56120247A (en) 1980-02-27 1980-02-27 Signal detection circuit

Publications (1)

Publication Number Publication Date
JPS56120247A true JPS56120247A (en) 1981-09-21

Family

ID=12116554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2365680A Pending JPS56120247A (en) 1980-02-27 1980-02-27 Signal detection circuit

Country Status (1)

Country Link
JP (1) JPS56120247A (en)

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