JPS5476116A - Signal interpolation circuit - Google Patents

Signal interpolation circuit

Info

Publication number
JPS5476116A
JPS5476116A JP14347577A JP14347577A JPS5476116A JP S5476116 A JPS5476116 A JP S5476116A JP 14347577 A JP14347577 A JP 14347577A JP 14347577 A JP14347577 A JP 14347577A JP S5476116 A JPS5476116 A JP S5476116A
Authority
JP
Japan
Prior art keywords
signal
error
inputted
sample
analog
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14347577A
Other languages
Japanese (ja)
Inventor
Sadanobu Ishida
Naohiro Tomikawa
Kiyomoto Nishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14347577A priority Critical patent/JPS5476116A/en
Publication of JPS5476116A publication Critical patent/JPS5476116A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1876—Interpolating methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Noise Elimination (AREA)

Abstract

PURPOSE:To enhance reliability and versatility with simple circuit constitution by converting digital signals to PAM signals and constituting a mean value interpolation circuit with analog circuits. CONSTITUTION:The digital signal corresponding to the PAM signal formed from analog signal is inputted to a D/A converter. When the signal e2 therein is repro- cuced by error, the sample error detection signal which has detected the error is inputted to a delay circuit 7 which in turn delays the sample holding signal so that the error point and the state before the wrong signal e2 is inputted to an analog switch 3b, i.e., the time when it is sample held in the analog switch 3a, coincide. The output thereof is then sent to a changeover switch 5, which sends the signal of 1/2(e1+e2) in place fo the wrong signal e2 to a buffer amplifier 2e. This signal is then held in the analog switch 3c by the next sample pulse and is outputted through a buffer amplifier 2f. Thereby, the reliability and versatility may be enhanced with the simple circuit constitution.
JP14347577A 1977-11-29 1977-11-29 Signal interpolation circuit Pending JPS5476116A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14347577A JPS5476116A (en) 1977-11-29 1977-11-29 Signal interpolation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14347577A JPS5476116A (en) 1977-11-29 1977-11-29 Signal interpolation circuit

Publications (1)

Publication Number Publication Date
JPS5476116A true JPS5476116A (en) 1979-06-18

Family

ID=15339555

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14347577A Pending JPS5476116A (en) 1977-11-29 1977-11-29 Signal interpolation circuit

Country Status (1)

Country Link
JP (1) JPS5476116A (en)

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