JPS56100460A - Bipolar mos semiconductor device and manufacture thereof - Google Patents

Bipolar mos semiconductor device and manufacture thereof

Info

Publication number
JPS56100460A
JPS56100460A JP206380A JP206380A JPS56100460A JP S56100460 A JPS56100460 A JP S56100460A JP 206380 A JP206380 A JP 206380A JP 206380 A JP206380 A JP 206380A JP S56100460 A JPS56100460 A JP S56100460A
Authority
JP
Japan
Prior art keywords
region
type
diffusely
mos
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP206380A
Other languages
Japanese (ja)
Inventor
Mikio Haijima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP206380A priority Critical patent/JPS56100460A/en
Publication of JPS56100460A publication Critical patent/JPS56100460A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the number of process and improve the degree of integration by forming diffusely a well region on the side of MOSFET and a region separating a bipolar transistor and MOS from each other simultaneously when the transistor and MOS are formed in the same semiconductor substrate. CONSTITUTION:In an n<-> type Si substrate 11 are formed diffusely n<+> type embodded regions 12a and 12b, whereon an n type layer 13 is made to grow epitaxially, while in one region 12a to form the MOS side the p<-> type well region 15 is formed diffusely in the layer 13. At the same time, the p<-> type separating region 16 surrounding the regions 12a and 12b are formed diffusely as far as it reaches the substrate 11, and the layer 13 is separated into islandlike parts containing the regions 12a and 12b respectively. Next, a p<+> type base region 17 is formed diffusely within the islandlike layer 13a on the bipolar side including the region 12b, while a ring-shaped p<+> type region 18 for preventing parasitic MOS is also formed diffusely within the separating region 16, and on the bipolar side an n<+> type emitter region 19 and a collector contact part 20 are provided simultaneously. In addition, on the MOS side, an n<+> type source region 21 and a drain region 22 are formed by simultaneous diffusion.
JP206380A 1980-01-14 1980-01-14 Bipolar mos semiconductor device and manufacture thereof Pending JPS56100460A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP206380A JPS56100460A (en) 1980-01-14 1980-01-14 Bipolar mos semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP206380A JPS56100460A (en) 1980-01-14 1980-01-14 Bipolar mos semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS56100460A true JPS56100460A (en) 1981-08-12

Family

ID=11518877

Family Applications (1)

Application Number Title Priority Date Filing Date
JP206380A Pending JPS56100460A (en) 1980-01-14 1980-01-14 Bipolar mos semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS56100460A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5864060A (en) * 1981-10-13 1983-04-16 Toshiba Corp Manufacture of semiconductor device
JPS63300553A (en) * 1987-05-29 1988-12-07 Nec Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5864060A (en) * 1981-10-13 1983-04-16 Toshiba Corp Manufacture of semiconductor device
JPS63300553A (en) * 1987-05-29 1988-12-07 Nec Corp Semiconductor device

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