JPS5587242A - Oscillation prevention system of digital adder - Google Patents

Oscillation prevention system of digital adder

Info

Publication number
JPS5587242A
JPS5587242A JP15866278A JP15866278A JPS5587242A JP S5587242 A JPS5587242 A JP S5587242A JP 15866278 A JP15866278 A JP 15866278A JP 15866278 A JP15866278 A JP 15866278A JP S5587242 A JPS5587242 A JP S5587242A
Authority
JP
Japan
Prior art keywords
output
adder
register
value
digital signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15866278A
Other languages
Japanese (ja)
Inventor
Masao Kasuga
Masaaki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP15866278A priority Critical patent/JPS5587242A/en
Priority to US06/095,554 priority patent/US4321685A/en
Publication of JPS5587242A publication Critical patent/JPS5587242A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To prevent oscillation caused by feeding a feedback signal to an adder without any restriction, by providing an intermediate register to the feedback loop of an adder which adds sequentially an output digital signal value before feedback to an input digital signal value.
CONSTITUTION: Electronic switch SW, having terminals 11 to 1n, are circularly connected by switching to apply digital signals to adder 2 in sequence. Its output F is applied to output register 4 and retained there by control pulses from terminal 5 while applied to total register 6. Intermediate register 9 maintains output signal R of output register 4 and fixes the value of digital signal Q of the 2nd input terminal of adder until output register 4 receives and holds the value of output F of adder 2.
COPYRIGHT: (C)1980,JPO&Japio
JP15866278A 1978-11-20 1978-12-25 Oscillation prevention system of digital adder Pending JPS5587242A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP15866278A JPS5587242A (en) 1978-12-25 1978-12-25 Oscillation prevention system of digital adder
US06/095,554 US4321685A (en) 1978-11-20 1979-11-19 Circuit for reducing the limit cycle in a digital filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15866278A JPS5587242A (en) 1978-12-25 1978-12-25 Oscillation prevention system of digital adder

Publications (1)

Publication Number Publication Date
JPS5587242A true JPS5587242A (en) 1980-07-01

Family

ID=15676601

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15866278A Pending JPS5587242A (en) 1978-11-20 1978-12-25 Oscillation prevention system of digital adder

Country Status (1)

Country Link
JP (1) JPS5587242A (en)

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