JPS5572273A - Multi-cpu system - Google Patents

Multi-cpu system

Info

Publication number
JPS5572273A
JPS5572273A JP14546578A JP14546578A JPS5572273A JP S5572273 A JPS5572273 A JP S5572273A JP 14546578 A JP14546578 A JP 14546578A JP 14546578 A JP14546578 A JP 14546578A JP S5572273 A JPS5572273 A JP S5572273A
Authority
JP
Japan
Prior art keywords
access
memory
arrival
send
cpu1
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14546578A
Other languages
Japanese (ja)
Inventor
Kenji Otsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP14546578A priority Critical patent/JPS5572273A/en
Publication of JPS5572273A publication Critical patent/JPS5572273A/en
Pending legal-status Critical Current

Links

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  • Multi Processors (AREA)

Abstract

PURPOSE: To make it possible to attain high-efficiency access by allowing a memory handle access requests from several CPUs in the order of arrival or on the prescribed preference basis when they arrive at the same time.
CONSTITUTION: When CPUs 1 and 2 share memory 3, CPU2 is considered to send an access request right after CPU1. In this case, memory 3 allows memory access in the order of arrival or on the prescribed preference basis in case of simultaneous arrival, after access from CPU1 ends, an access end signal will be sent out. consequently, CPU can send an access request at any point in time, so that highly- efficient access can be attained.
COPYRIGHT: (C)1980,JPO&Japio
JP14546578A 1978-11-25 1978-11-25 Multi-cpu system Pending JPS5572273A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14546578A JPS5572273A (en) 1978-11-25 1978-11-25 Multi-cpu system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14546578A JPS5572273A (en) 1978-11-25 1978-11-25 Multi-cpu system

Publications (1)

Publication Number Publication Date
JPS5572273A true JPS5572273A (en) 1980-05-30

Family

ID=15385859

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14546578A Pending JPS5572273A (en) 1978-11-25 1978-11-25 Multi-cpu system

Country Status (1)

Country Link
JP (1) JPS5572273A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01239664A (en) * 1988-03-22 1989-09-25 Nec Corp Common memory arbitration device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53114641A (en) * 1977-03-16 1978-10-06 Ibm Multiple processing system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53114641A (en) * 1977-03-16 1978-10-06 Ibm Multiple processing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01239664A (en) * 1988-03-22 1989-09-25 Nec Corp Common memory arbitration device

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