JPS5567263A - Channel synchronizing system of time division exchange - Google Patents

Channel synchronizing system of time division exchange

Info

Publication number
JPS5567263A
JPS5567263A JP14140178A JP14140178A JPS5567263A JP S5567263 A JPS5567263 A JP S5567263A JP 14140178 A JP14140178 A JP 14140178A JP 14140178 A JP14140178 A JP 14140178A JP S5567263 A JPS5567263 A JP S5567263A
Authority
JP
Japan
Prior art keywords
memory
speed
channel
circuit
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14140178A
Other languages
Japanese (ja)
Other versions
JPS5741877B2 (en
Inventor
Kenji Miyayasu
Tetsuhiro Nomura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP14140178A priority Critical patent/JPS5567263A/en
Publication of JPS5567263A publication Critical patent/JPS5567263A/en
Publication of JPS5741877B2 publication Critical patent/JPS5741877B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To make use of a low-speed memory possible and extend the extension block unit of a synchronizing unit by providing a delay circuit between a multiplexing circuit and a buffer memory to reduce the operation cycle of the synchronizing unit. CONSTITUTION:Data of each incoming highway HW1 is subjected to time division multiplexing in 3 through frame signal extraction and series-parallel conversion part 2 and is supplied to buffer memory 5 through high-speed HW4 and delay circuit 12. Frame signals are given channel synchronizing unit 10, and each channel address of incoming HW1 in the office is generated and is given to holding memory 11 for channel conversion through distributing circuit 13. Output information of memory 11 is caused to agree with the phase of data on HW4 to perform read and write to memory 5, and then, channel conversion is performed in memory 5, and data is transmitted to high-speed outgoing HW9 through high-speed HW6, separator circuit 7, and parallel-series conversion part 8. As a result, the operation cycle of unit 10 is reduced to the half.
JP14140178A 1978-11-16 1978-11-16 Channel synchronizing system of time division exchange Granted JPS5567263A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14140178A JPS5567263A (en) 1978-11-16 1978-11-16 Channel synchronizing system of time division exchange

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14140178A JPS5567263A (en) 1978-11-16 1978-11-16 Channel synchronizing system of time division exchange

Publications (2)

Publication Number Publication Date
JPS5567263A true JPS5567263A (en) 1980-05-21
JPS5741877B2 JPS5741877B2 (en) 1982-09-06

Family

ID=15291137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14140178A Granted JPS5567263A (en) 1978-11-16 1978-11-16 Channel synchronizing system of time division exchange

Country Status (1)

Country Link
JP (1) JPS5567263A (en)

Also Published As

Publication number Publication date
JPS5741877B2 (en) 1982-09-06

Similar Documents

Publication Publication Date Title
ES8201379A1 (en) Rapid message transmission system between computers
JPS5567263A (en) Channel synchronizing system of time division exchange
EP0150540A3 (en) Method for data communication as well as a station for carrying out the method
JPS54132135A (en) Memory control unit
JPH0666749B2 (en) Branch circuit
JPS5549095A (en) Memory switch channel system
JPS5429908A (en) Transmission control system in signal transmission system
FR2265227A1 (en) Time multiplex exchange for binarily coded signals - which have different transmission speeds and uses topographic tables
JPS5255406A (en) Memory switch system
JPS55117779A (en) Buffer control system
JP2770375B2 (en) Transmission delay phase compensation circuit
GB1269872A (en) Scanning circuits in a central telecommunication exchange
JPS57125425A (en) System for information transmission
JPS54125904A (en) Interface circuit system for digital multiple lines suited to time-dividion exchange
JPH0714155B2 (en) PCM terminal equipment
JPS54115006A (en) Time sharing exchanging system
JPS5683157A (en) Synchronizer
JPS54508A (en) Spare system for exchange control system
JPS5799095A (en) Memory switch control system of same speed in small bundle
JPS61121597A (en) Time division channel system and equipment thereof
JPS55159692A (en) Intraoffice call connection system for time sharing exchanger remote station
JPH0750874B2 (en) Format conversion device
JPS614393A (en) Time switching circuit
JPS5614346A (en) Write and read system for frame memory unit
GB1481393A (en) Information processing systems