JPS54125904A - Interface circuit system for digital multiple lines suited to time-dividion exchange - Google Patents

Interface circuit system for digital multiple lines suited to time-dividion exchange

Info

Publication number
JPS54125904A
JPS54125904A JP3291778A JP3291778A JPS54125904A JP S54125904 A JPS54125904 A JP S54125904A JP 3291778 A JP3291778 A JP 3291778A JP 3291778 A JP3291778 A JP 3291778A JP S54125904 A JPS54125904 A JP S54125904A
Authority
JP
Japan
Prior art keywords
exchange
circuits
frame
transmission lines
dividion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3291778A
Other languages
Japanese (ja)
Inventor
Hideki Nakane
Takehiko Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3291778A priority Critical patent/JPS54125904A/en
Publication of JPS54125904A publication Critical patent/JPS54125904A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To reduce the transmission delay and thus to increase the performance by reading out the data synchronized with the frame phase within the exchange with the timing determined corresponding to the plural digital multiple transmission lines through the frame aligner circuit. CONSTITUTION:Reception pulse generator circuits 1-1-1-n receive the multiple signals from plural digital transmission lines to convert them into the reception pulses for the exchange. And frame aligner circuits 2'-1-2'-n receive the output pulses from circuits 1-1-1-n and convert the pulse phases into the frame phases within the exchange respectively. Then the data synchronized with the frame phase within the exchange is read out with the timing of generator circuit 6 which is determined in accordance with the plural digital transmission lines sent from the frame phase synchronous memory provided within circuits 2'-1-2'-n each, and then the data read out is introduced to circuit network highway HW of the exchange in the form of the sum of the data output. As a result, the transmission delay is reduced thus to increase the performance.
JP3291778A 1978-03-24 1978-03-24 Interface circuit system for digital multiple lines suited to time-dividion exchange Pending JPS54125904A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3291778A JPS54125904A (en) 1978-03-24 1978-03-24 Interface circuit system for digital multiple lines suited to time-dividion exchange

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3291778A JPS54125904A (en) 1978-03-24 1978-03-24 Interface circuit system for digital multiple lines suited to time-dividion exchange

Publications (1)

Publication Number Publication Date
JPS54125904A true JPS54125904A (en) 1979-09-29

Family

ID=12372240

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3291778A Pending JPS54125904A (en) 1978-03-24 1978-03-24 Interface circuit system for digital multiple lines suited to time-dividion exchange

Country Status (1)

Country Link
JP (1) JPS54125904A (en)

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