JPS5566041A - Extension system of storage capacity - Google Patents

Extension system of storage capacity

Info

Publication number
JPS5566041A
JPS5566041A JP13788478A JP13788478A JPS5566041A JP S5566041 A JPS5566041 A JP S5566041A JP 13788478 A JP13788478 A JP 13788478A JP 13788478 A JP13788478 A JP 13788478A JP S5566041 A JPS5566041 A JP S5566041A
Authority
JP
Japan
Prior art keywords
capacity
storage device
storage capacity
bus
instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13788478A
Other languages
Japanese (ja)
Inventor
Kenji Ando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13788478A priority Critical patent/JPS5566041A/en
Publication of JPS5566041A publication Critical patent/JPS5566041A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To extend a storage capacity without damaging a high-speed property by connecting an internal storage device and an extension storage device to the same memory bus line and selecting information communication between the extension storage device and a processing unit with I/O instructions.
CONSTITUTION: This system is constituted by processing unit 1 which transmits or receives information to or from internal storage device of a storage capacity of n-number words connected to memory bus line 7, extension storage device blocks E1WEi5 of a storage capacity of m-number words connected to the same bus 7, and block selection circuit 9 which generates signals to select blocks E1WEi. The total sum of capacity n of device 3 and capacity m per one block of device 5 is set to a value below the maximum storage capacity which can be designated directly by bus 7 of unit 1. In respect to a program to select blocks of device 5, I/O instructions or instructions corresponding to them are stored in device 3 previously and are given to circuit 6 through I/O interface bus line 6. One of selection signal lines 8 is selected by circuit 6, and one block of device 5 is connected to bus 7, thereby extending the memory capacity.
COPYRIGHT: (C)1980,JPO&Japio
JP13788478A 1978-11-10 1978-11-10 Extension system of storage capacity Pending JPS5566041A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13788478A JPS5566041A (en) 1978-11-10 1978-11-10 Extension system of storage capacity

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13788478A JPS5566041A (en) 1978-11-10 1978-11-10 Extension system of storage capacity

Publications (1)

Publication Number Publication Date
JPS5566041A true JPS5566041A (en) 1980-05-19

Family

ID=15208928

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13788478A Pending JPS5566041A (en) 1978-11-10 1978-11-10 Extension system of storage capacity

Country Status (1)

Country Link
JP (1) JPS5566041A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55164955A (en) * 1979-05-09 1980-12-23 Nec Corp Information processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55164955A (en) * 1979-05-09 1980-12-23 Nec Corp Information processor

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