JPS54154945A - Memory circuit - Google Patents

Memory circuit

Info

Publication number
JPS54154945A
JPS54154945A JP6364978A JP6364978A JPS54154945A JP S54154945 A JPS54154945 A JP S54154945A JP 6364978 A JP6364978 A JP 6364978A JP 6364978 A JP6364978 A JP 6364978A JP S54154945 A JPS54154945 A JP S54154945A
Authority
JP
Japan
Prior art keywords
memory circuit
output
memory cell
wires
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6364978A
Other languages
Japanese (ja)
Inventor
Mamoru Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6364978A priority Critical patent/JPS54154945A/en
Publication of JPS54154945A publication Critical patent/JPS54154945A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To obtain a memory circuit suited for the associative memory which carries out the input and output through the designated memory cell by distributing the memory cell on the orthogonal wiring and then giving the necessary information.
CONSTITUTION: With application of retrieving input A and B to the 4×4 associative memory circuit, logic 0 or 1 is obtained at output line wires W0WW3 via decoder 411. As a result, logic 1 is secured to that the W wire of which features 1 for the product member among S0WS7 connected to wires W0WW3. For example, S1WS4 plus S7 feature 1. Just one piece of the row wires is selected via selection signal 821. With selection of row wire S1, output R1 is selected through selection circuit 52. With this output data Ri is obtained from the memory circuit. In other words, an optical product member is generated to the retrieving input based on the contents of the memory cell group.
COPYRIGHT: (C)1979,JPO&Japio
JP6364978A 1978-05-26 1978-05-26 Memory circuit Pending JPS54154945A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6364978A JPS54154945A (en) 1978-05-26 1978-05-26 Memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6364978A JPS54154945A (en) 1978-05-26 1978-05-26 Memory circuit

Publications (1)

Publication Number Publication Date
JPS54154945A true JPS54154945A (en) 1979-12-06

Family

ID=13235399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6364978A Pending JPS54154945A (en) 1978-05-26 1978-05-26 Memory circuit

Country Status (1)

Country Link
JP (1) JPS54154945A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60157799A (en) * 1983-09-22 1985-08-19 デイジタル　イクイプメント　コ−ポレ−シヨン Memory subsystem
JPS61107597A (en) * 1984-10-29 1986-05-26 テキサス　インスツルメンツ　インコーポレイテツド Block association memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60157799A (en) * 1983-09-22 1985-08-19 デイジタル　イクイプメント　コ−ポレ−シヨン Memory subsystem
JPS6349319B2 (en) * 1983-09-22 1988-10-04 Digital Equipment Corp
JPS61107597A (en) * 1984-10-29 1986-05-26 テキサス　インスツルメンツ　インコーポレイテツド Block association memory

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