JPS5562762A - Semiconductor device - Google Patents

Abstract

PURPOSE: To advantageously design a semiconductor device by approaching the current amplification factor, saturated resistance and maximum current or the like characteristics of a PNP transistor to an NPN transistor in a complementary integrated circuit (IC).

CONSTITUTION: A substrate 32 superimposed with N-type epitaxial layers 26, 31 on a P-type silicon layer 21 is isolated via P-type layers 25a∼25c, in a PNP transistor an emitter is formed by a layer 34, a base is by a layer 37, and a collector by a buried layer 24, and in an NPN transistor 40 an emitter is formed by a layer 38, a base by a buried layer 39, and a collector by layer 41 outside the layers 29, 33. Since the buried layer 30 of high density is interposed between the layers 26 and 31 in a transistor 39, it is difficult to punch through the emitter and the collector. The layer 30 is separated from the buried layer 24 to enhance the dielectric strength between the emitter and the collector thereof. Since a high density layer 28 is provided regardless of the base 29 of the NPN transistor 40 between the buried layer 24 and the collector electrode 42C, its saturated resistance is decreased for large current. Thus, the characteristics of both the transistor can approach to each other.

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