JPS5561146A - Exclusive logical sum circuit - Google Patents

Exclusive logical sum circuit

Info

Publication number
JPS5561146A
JPS5561146A JP13390178A JP13390178A JPS5561146A JP S5561146 A JPS5561146 A JP S5561146A JP 13390178 A JP13390178 A JP 13390178A JP 13390178 A JP13390178 A JP 13390178A JP S5561146 A JPS5561146 A JP S5561146A
Authority
JP
Japan
Prior art keywords
inputs
logical sum
exclusive logical
nand
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13390178A
Other languages
Japanese (ja)
Inventor
Mitsuo Tsuruta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13390178A priority Critical patent/JPS5561146A/en
Publication of JPS5561146A publication Critical patent/JPS5561146A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To increase the operation speed with less number of operation stages and with simplified circuit constitution through the decrease in the number of gate used, by constitution of 3 inputs and 4 stages for 8 sets of the same types of exclusive logical sum circuits. CONSTITUTION:Three inputs(a,b,c) are given to the NAND gare 3N11 to produce the output X1, and three inputs (a,b,X1)(a,X1,c) are given to the NAND gates 3N12,3N13,3N14 to produce outputs X2...X4. Further, three inputs (a,X2,X3), (X3, X4,c), (X2,b,X4) are given to the NAND gates 3N15,3N16,3N17 to output X5,X6, X7 and the NAND gare 3N18 outputs the inversion of exclusive logical sum a+b+c from the input (X5,X6,X7). Thus, the number of gares used is reduced and the circuit constitution is simple by using only the same type of gates, the number of operation stages is made less, to increase the operation speed.
JP13390178A 1978-10-31 1978-10-31 Exclusive logical sum circuit Pending JPS5561146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13390178A JPS5561146A (en) 1978-10-31 1978-10-31 Exclusive logical sum circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13390178A JPS5561146A (en) 1978-10-31 1978-10-31 Exclusive logical sum circuit

Publications (1)

Publication Number Publication Date
JPS5561146A true JPS5561146A (en) 1980-05-08

Family

ID=15115741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13390178A Pending JPS5561146A (en) 1978-10-31 1978-10-31 Exclusive logical sum circuit

Country Status (1)

Country Link
JP (1) JPS5561146A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0621695A2 (en) * 1993-04-19 1994-10-26 Motorola, Inc. Integrated circuit with an active-level configurable pin and method therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0621695A2 (en) * 1993-04-19 1994-10-26 Motorola, Inc. Integrated circuit with an active-level configurable pin and method therefor
EP0621695A3 (en) * 1993-04-19 1997-09-17 Motorola Inc Integrated circuit with an active-level configurable pin and method therefor.

Similar Documents

Publication Publication Date Title
JPS5561146A (en) Exclusive logical sum circuit
GB958884A (en) General purpose majority-decision logic arrays
JPS5352386A (en) Semiconductor integrated circuit
JPS54154964A (en) Programable counter
JPS52123182A (en) Input and output end protection system
Protter Asymptotic behavior of solutions of hyperbolic inequalities
JPS54143056A (en) Variable frequency divider circuit
JPS52140241A (en) Binary #-digit addition circuit
JPS57109427A (en) Semiconductor integrated circuit device
JPS5518706A (en) Parallel adder circuit
JPS539450A (en) Primary digital overall areas passing circuit
JPS52116129A (en) Logical circuit
JPS55164942A (en) Division circuit
JPS5696328A (en) Logical arithmetic operating device
JPS57114946A (en) Microprogram controller
JPS6424516A (en) Crc check circuit
JPS56147236A (en) Adding circuit
JPS54107664A (en) Programmable counter
JPS55145431A (en) A/d converter
FR2410914A2 (en) Logic element for frequency divider - has FET circuit acting as coincidence gate in each stage of divider
JPS5352348A (en) Cmos input circuit
JPS5382253A (en) Logical operation circuit
JPS5725744A (en) Interleaving circuit
JPS5373951A (en) Flip-flop circuit
JPS52153344A (en) Arithmetic display unit