JPS5559579A - Sequence controller - Google Patents

Abstract

PURPOSE: To obtain a sequence controller which prevents the lowering of the process speed of the logic arithmetic processor by installing two arithmetic processors plus the common RAM which is given the access by those arithmetic processors.

CONSTITUTION: Input/output address (a) and output data (a') are supplied to input/output bus 5 from logic arithmetic processor 1A, and also supplied to one side of selection circuit 7. The other input of circuit 7 is for input/output address (c) and output data (c') of auxiliary arithmetic processor 1B. Address (c) which gives an address to RAM4 is generaed at processor 1B to be detected by decoder 8, and thus high-level signal (d) is supplied to timing circuit 9. Circuit 9, receiving signal (d), turns off ready signal (e) to be sent to 1B to stop the action of 1B as well as turn signal (s) to a high level. Thus circuit 7 selects signals (c) and (c') for processor 1B and then supplied them to RAM4 in the form of signals (f) and (f'). Generally, input data (b) is set up after sending signal (a) to bus 5.

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