JPS5559579A - Sequence controller - Google Patents
Sequence controllerInfo
- Publication number
- JPS5559579A JPS5559579A JP13149078A JP13149078A JPS5559579A JP S5559579 A JPS5559579 A JP S5559579A JP 13149078 A JP13149078 A JP 13149078A JP 13149078 A JP13149078 A JP 13149078A JP S5559579 A JPS5559579 A JP S5559579A
- Authority
- JP
- Japan
- Prior art keywords
- input
- circuit
- supplied
- processor
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Programmable Controllers (AREA)
Abstract
PURPOSE: To obtain a sequence controller which prevents the lowering of the process speed of the logic arithmetic processor by installing two arithmetic processors plus the common RAM which is given the access by those arithmetic processors.
CONSTITUTION: Input/output address (a) and output data (a') are supplied to input/output bus 5 from logic arithmetic processor 1A, and also supplied to one side of selection circuit 7. The other input of circuit 7 is for input/output address (c) and output data (c') of auxiliary arithmetic processor 1B. Address (c) which gives an address to RAM4 is generaed at processor 1B to be detected by decoder 8, and thus high-level signal (d) is supplied to timing circuit 9. Circuit 9, receiving signal (d), turns off ready signal (e) to be sent to 1B to stop the action of 1B as well as turn signal (s) to a high level. Thus circuit 7 selects signals (c) and (c') for processor 1B and then supplied them to RAM4 in the form of signals (f) and (f'). Generally, input data (b) is set up after sending signal (a) to bus 5.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13149078A JPS5559579A (en) | 1978-10-27 | 1978-10-27 | Sequence controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13149078A JPS5559579A (en) | 1978-10-27 | 1978-10-27 | Sequence controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5559579A true JPS5559579A (en) | 1980-05-06 |
Family
ID=15059204
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13149078A Pending JPS5559579A (en) | 1978-10-27 | 1978-10-27 | Sequence controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5559579A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57206906A (en) * | 1981-06-15 | 1982-12-18 | Hitachi Ltd | Operation controlling device |
JPS5840619A (en) * | 1981-09-04 | 1983-03-09 | Hitachi Ltd | Sequence controller and its control method |
JPS5965307A (en) * | 1982-10-06 | 1984-04-13 | Canon Inc | Sequence controller |
JPS5965306A (en) * | 1982-10-06 | 1984-04-13 | Canon Inc | Sequence controller |
-
1978
- 1978-10-27 JP JP13149078A patent/JPS5559579A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57206906A (en) * | 1981-06-15 | 1982-12-18 | Hitachi Ltd | Operation controlling device |
JPS5840619A (en) * | 1981-09-04 | 1983-03-09 | Hitachi Ltd | Sequence controller and its control method |
JPS5965307A (en) * | 1982-10-06 | 1984-04-13 | Canon Inc | Sequence controller |
JPS5965306A (en) * | 1982-10-06 | 1984-04-13 | Canon Inc | Sequence controller |
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