JPS5558647A - Coordinate signal generation circuit system - Google Patents

Coordinate signal generation circuit system

Info

Publication number
JPS5558647A
JPS5558647A JP13203478A JP13203478A JPS5558647A JP S5558647 A JPS5558647 A JP S5558647A JP 13203478 A JP13203478 A JP 13203478A JP 13203478 A JP13203478 A JP 13203478A JP S5558647 A JPS5558647 A JP S5558647A
Authority
JP
Japan
Prior art keywords
register
coordinate value
clock pulse
stored
equalizer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13203478A
Other languages
Japanese (ja)
Other versions
JPS5752746B2 (en
Inventor
Yasukazu Ito
Kazuo Murano
Shigeyuki Umigami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13203478A priority Critical patent/JPS5558647A/en
Publication of JPS5558647A publication Critical patent/JPS5558647A/en
Publication of JPS5752746B2 publication Critical patent/JPS5752746B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE: To reduce the number of coordinate signal lines, etc., to simplify a circuit by storing the y coordinate value from an equalizer into one register by a clock pulse and transferring the x coordinate value, which was stored by the preceding clock pulse, to the other register.
CONSTITUTION: Receiving input signals are demodulated by multiplying cos ωct and sin ωct and become x and y coordiante value signals. Then, higher components are eliminated by LPF 1 and 2, and waveforme distortion is eliminated by equalizer 11, and after that, the transmission signal point is decided by decision circuit 12. In this case, x coordinate value x1 is temporarily stored in register 13 by a clock pulse from clock generator 14, and y coordinate value y1 from equalizer 11 is stored in register 13 by the next clock pulse, and simultaneously, coordinate value x1 is transferred to register 15. Then, digital values stored in registers 13 and 15 are converted to analogue values by D/A converters 16 and 17 and are displayed on oscilloscope 10. As a result, the number of coordinate signal lines, etc., can be reduced to simplyfy the circuit.
COPYRIGHT: (C)1980,JPO&Japio
JP13203478A 1978-10-26 1978-10-26 Coordinate signal generation circuit system Granted JPS5558647A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13203478A JPS5558647A (en) 1978-10-26 1978-10-26 Coordinate signal generation circuit system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13203478A JPS5558647A (en) 1978-10-26 1978-10-26 Coordinate signal generation circuit system

Publications (2)

Publication Number Publication Date
JPS5558647A true JPS5558647A (en) 1980-05-01
JPS5752746B2 JPS5752746B2 (en) 1982-11-09

Family

ID=15071944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13203478A Granted JPS5558647A (en) 1978-10-26 1978-10-26 Coordinate signal generation circuit system

Country Status (1)

Country Link
JP (1) JPS5558647A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0454457U (en) * 1990-09-13 1992-05-11

Also Published As

Publication number Publication date
JPS5752746B2 (en) 1982-11-09

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