JPS554906A - Semi-conductor manufacturing method - Google Patents

Semi-conductor manufacturing method

Info

Publication number
JPS554906A
JPS554906A JP7645978A JP7645978A JPS554906A JP S554906 A JPS554906 A JP S554906A JP 7645978 A JP7645978 A JP 7645978A JP 7645978 A JP7645978 A JP 7645978A JP S554906 A JPS554906 A JP S554906A
Authority
JP
Japan
Prior art keywords
film
substrate
nonmetal
supplied
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7645978A
Other languages
Japanese (ja)
Inventor
Hideki Yasuoka
Motofumi Masaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7645978A priority Critical patent/JPS554906A/en
Publication of JPS554906A publication Critical patent/JPS554906A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain shallow, uniform p-n junction quickly by supplying p-type ions to an area adjoining non-metalic film after n-type ions are supplied to the other side of the film.
CONSTITUTION: N-type ion impurities are supplied into a semi-conductor substrate either after providing a thin film of non-cristalline nonmetal or nonmetal that has different crystal orientation or lattice constant than the substrate on the substrate, or directly to the substrate without providing the film. By applying the CVD metod, an additional film of non-cristalline nonmetal of a film having different cristal orientation or lattice constant then the substrate is laied on, and p-type ion impurities are supplied through the CVD film to obtain p-n junction. By so doing, the position where density of p-type ion impurities is the maximum becomes shallower, thus forming the p-n junction which has a negative density gradient.
COPYRIGHT: (C)1980,JPO&Japio
JP7645978A 1978-06-26 1978-06-26 Semi-conductor manufacturing method Pending JPS554906A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7645978A JPS554906A (en) 1978-06-26 1978-06-26 Semi-conductor manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7645978A JPS554906A (en) 1978-06-26 1978-06-26 Semi-conductor manufacturing method

Publications (1)

Publication Number Publication Date
JPS554906A true JPS554906A (en) 1980-01-14

Family

ID=13605732

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7645978A Pending JPS554906A (en) 1978-06-26 1978-06-26 Semi-conductor manufacturing method

Country Status (1)

Country Link
JP (1) JPS554906A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50143463A (en) * 1974-05-08 1975-11-18

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50143463A (en) * 1974-05-08 1975-11-18

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