JPS5541751A - Manufacturing semiconductor device - Google Patents

Manufacturing semiconductor device

Info

Publication number
JPS5541751A
JPS5541751A JP11498178A JP11498178A JPS5541751A JP S5541751 A JPS5541751 A JP S5541751A JP 11498178 A JP11498178 A JP 11498178A JP 11498178 A JP11498178 A JP 11498178A JP S5541751 A JPS5541751 A JP S5541751A
Authority
JP
Japan
Prior art keywords
layer
groove
film
deposited
films
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11498178A
Other languages
Japanese (ja)
Inventor
Tomihisa Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11498178A priority Critical patent/JPS5541751A/en
Publication of JPS5541751A publication Critical patent/JPS5541751A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: To enhance contacting property with a substrate by specifying the thickness of an Mo film to 500W1,500Å in the case electrodes comprising 4-layer metal films are formed by stacking and heat-treating Al, Mo, Ni, and Au on a semiconductor substrate in this order.
CONSTITUTION: N-type base layer 2 and P-type base layer 3 are stacked on a P-type emitter layer 1, and a circular N-type emitter region 4 is diffused in the layer 3. Then, a mesa groove 6 which reaches the layer 2 is provided in such a way to surround the region 4 on the side of the layer 3, and another groove 7 which reaches the layer 2 is also provided on the side of the layer 1 in such a way to oppose the groove 6. Thereafter, a glass film 8 is deposited on the inside of the groove 6, and a glass film 10 is deposited on the layers 3 and 4 which are surrounded by the grooves. The same treatment is made on the side of the groove 7. By using photoresi sts 12 and 13, the glass films in the specified areas are etched out, and a stacked metal film 21 comprising Al, Mo, Ni, and Au films 17W 20 are deposited on the etched-out area. At this time, the thickness of the Mo film 18 is specified, thereby the generation of intermetal compounds is prevented and contact property is enhanced.
COPYRIGHT: (C)1980,JPO&Japio
JP11498178A 1978-09-18 1978-09-18 Manufacturing semiconductor device Pending JPS5541751A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11498178A JPS5541751A (en) 1978-09-18 1978-09-18 Manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11498178A JPS5541751A (en) 1978-09-18 1978-09-18 Manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JPS5541751A true JPS5541751A (en) 1980-03-24

Family

ID=14651390

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11498178A Pending JPS5541751A (en) 1978-09-18 1978-09-18 Manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPS5541751A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745925A (en) * 1980-08-04 1982-03-16 Ibm Method of forming conductor
JP2006024829A (en) * 2004-07-09 2006-01-26 Toshiba Corp Semiconductor device and its manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745925A (en) * 1980-08-04 1982-03-16 Ibm Method of forming conductor
JP2006024829A (en) * 2004-07-09 2006-01-26 Toshiba Corp Semiconductor device and its manufacturing method
US7964939B2 (en) 2004-07-09 2011-06-21 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing same

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