JPS5537673A - Connection system of input-output device - Google Patents

Connection system of input-output device

Info

Publication number
JPS5537673A
JPS5537673A JP11092478A JP11092478A JPS5537673A JP S5537673 A JPS5537673 A JP S5537673A JP 11092478 A JP11092478 A JP 11092478A JP 11092478 A JP11092478 A JP 11092478A JP S5537673 A JPS5537673 A JP S5537673A
Authority
JP
Japan
Prior art keywords
input
line
cpu1
output
checker
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11092478A
Other languages
Japanese (ja)
Inventor
Haruka Nakamura
Harumitsu Yoshioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP11092478A priority Critical patent/JPS5537673A/en
Publication of JPS5537673A publication Critical patent/JPS5537673A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To eliminate the need for a testing cable or checker, etc., and also to simplify the connection of a control signal by making the immediate test of an input-output control part by changing a computer unit over to an input-output device.
CONSTITUTION: When computer unit CPU1 and input-output device 3 are connected together via terminals 4 and 4' of a connector, the relation between terminal 4 at the CPU1 side and device 3 is so fixed that respecitve lines 5,5'...10, 10' are constituted into a mutual series circuit. Further, when CPU1 is disconnected from device 3, output line 5 and input line 8, command line 6 and input strobe line 9, and output mode line 7 and status line 10 are respectively connected by folded circuits. To connect CPU1 to a checker, the same connections as mentioned above are made in the internal checker part to eliminate the need for cables for testing, the connections of control signals.
COPYRIGHT: (C)1980,JPO&Japio
JP11092478A 1978-09-09 1978-09-09 Connection system of input-output device Pending JPS5537673A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11092478A JPS5537673A (en) 1978-09-09 1978-09-09 Connection system of input-output device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11092478A JPS5537673A (en) 1978-09-09 1978-09-09 Connection system of input-output device

Publications (1)

Publication Number Publication Date
JPS5537673A true JPS5537673A (en) 1980-03-15

Family

ID=14548062

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11092478A Pending JPS5537673A (en) 1978-09-09 1978-09-09 Connection system of input-output device

Country Status (1)

Country Link
JP (1) JPS5537673A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57141303U (en) * 1981-02-28 1982-09-04
JPS6160164A (en) * 1984-08-31 1986-03-27 Nec Corp Data transfer device
JPH0340012A (en) * 1990-07-12 1991-02-20 Seiko Epson Corp Connecting system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57141303U (en) * 1981-02-28 1982-09-04
JPS6160164A (en) * 1984-08-31 1986-03-27 Nec Corp Data transfer device
JPH0340012A (en) * 1990-07-12 1991-02-20 Seiko Epson Corp Connecting system

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