JPS5529115A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5529115A
JPS5529115A JP10179078A JP10179078A JPS5529115A JP S5529115 A JPS5529115 A JP S5529115A JP 10179078 A JP10179078 A JP 10179078A JP 10179078 A JP10179078 A JP 10179078A JP S5529115 A JPS5529115 A JP S5529115A
Authority
JP
Japan
Prior art keywords
layer
diffusion
fet
psg
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10179078A
Other languages
Japanese (ja)
Other versions
JPS639387B2 (en
Inventor
Yasunobu Tanizaki
Akira Muramatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10179078A priority Critical patent/JPS5529115A/en
Publication of JPS5529115A publication Critical patent/JPS5529115A/en
Publication of JPS639387B2 publication Critical patent/JPS639387B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To lessen the variation of the threshold and offset voltage of FET's through the process consisting of oxidizing the gate of said FET's after removing the PSG and P-diffusion layer formed on the diffusion of the emitter of a dipolar transistor and making a given mode of P-treatment.
CONSTITUTION: The n-type buried layer 5, n-epitaxial layer 4 and separated layer 13 are made in and on a p-type substrate 6. Next, the base 9 of an npn dipolar element, and the source 7, drain 8 and emitter 2 of an FET are made. The PSG layer 1 and p-diffusion layer 10 formed at this time are completely removed through etching. Next, the 10∼100Å PSG layer is formed at 700∼900°C after gate oxidation. The flow of P is selected so that the concentration of P may become 1∼10 mol%, and diffusion is made at 1,000°C for a short period of time after deposition. Thereafter, selective opening is made in the SiO2 film on the surface, and an Al electrode is attached. The dispersion of the threshold voltage and the variation of the offset voltage of this IC are small during both normal temperature and high temperature bias operations.
COPYRIGHT: (C)1980,JPO&Japio
JP10179078A 1978-08-23 1978-08-23 Manufacture of semiconductor device Granted JPS5529115A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10179078A JPS5529115A (en) 1978-08-23 1978-08-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10179078A JPS5529115A (en) 1978-08-23 1978-08-23 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5529115A true JPS5529115A (en) 1980-03-01
JPS639387B2 JPS639387B2 (en) 1988-02-29

Family

ID=14309954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10179078A Granted JPS5529115A (en) 1978-08-23 1978-08-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5529115A (en)

Also Published As

Publication number Publication date
JPS639387B2 (en) 1988-02-29

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