JPS5524429A - Punch-through type constant-voltage diode and its manufacturing method - Google Patents

Punch-through type constant-voltage diode and its manufacturing method

Info

Publication number
JPS5524429A
JPS5524429A JP9683778A JP9683778A JPS5524429A JP S5524429 A JPS5524429 A JP S5524429A JP 9683778 A JP9683778 A JP 9683778A JP 9683778 A JP9683778 A JP 9683778A JP S5524429 A JPS5524429 A JP S5524429A
Authority
JP
Japan
Prior art keywords
layer
punch
type
sio
growth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9683778A
Other languages
Japanese (ja)
Inventor
Kenji Mitsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9683778A priority Critical patent/JPS5524429A/en
Publication of JPS5524429A publication Critical patent/JPS5524429A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE: To minimize a dispersion of punch-through voltage due to the thickness of P epitaxial layer by suppressing a growth of depletion layer with P+ layer provided uniformly in the thickness direction of P type Si epitaxial layer.
CONSTITUTION: P+ ion-impregnated layer 9 and P- epitaxial layer 2 are laminated on N type Si substrate 1. The layer 2 is isolated with N type layer 4 provided by SiO2 mask 3. An opening is then arranged in SiO2 on the layer 2 and P+ layer 10 is formed to reach P+ layer 9. Next, SiO2 is again subjected to a selective opening to form N type emitter layer 5, covered with a protective film 6 and then subjected to a selective opening to attach an electrode 7. According to this constitution, P+ layer 9 suppresses the growth of a depletion layer almost all against voltage applied, and a dispersion in punch-through voltage of constant-voltage diode is minimized accordingly. Further P+ layer 10 is effective enough to minimize the growth of depletion layer on the emitter N layer 5 at its end and develop it at the center to punch-through, thus decreasing dispersion under suppressing abnormal punch- through.
COPYRIGHT: (C)1980,JPO&Japio
JP9683778A 1978-08-09 1978-08-09 Punch-through type constant-voltage diode and its manufacturing method Pending JPS5524429A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9683778A JPS5524429A (en) 1978-08-09 1978-08-09 Punch-through type constant-voltage diode and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9683778A JPS5524429A (en) 1978-08-09 1978-08-09 Punch-through type constant-voltage diode and its manufacturing method

Publications (1)

Publication Number Publication Date
JPS5524429A true JPS5524429A (en) 1980-02-21

Family

ID=14175630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9683778A Pending JPS5524429A (en) 1978-08-09 1978-08-09 Punch-through type constant-voltage diode and its manufacturing method

Country Status (1)

Country Link
JP (1) JPS5524429A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4646118A (en) * 1983-12-13 1987-02-24 Fujitsu Limited Semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4646118A (en) * 1983-12-13 1987-02-24 Fujitsu Limited Semiconductor memory device

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