JPS55165661A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS55165661A JPS55165661A JP7371879A JP7371879A JPS55165661A JP S55165661 A JPS55165661 A JP S55165661A JP 7371879 A JP7371879 A JP 7371879A JP 7371879 A JP7371879 A JP 7371879A JP S55165661 A JPS55165661 A JP S55165661A
- Authority
- JP
- Japan
- Prior art keywords
- pads
- elements
- packages
- semiconductor
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
PURPOSE:To reduce the number of parts and cost, by connecting semiconductor elements with terminal pads and attaching the elements to a terminal board having external leads at prescribed intervals, in stacking the semiconductor elements. CONSTITUTION:Semiconductor memory elements 1 for an ROM, an RAM or the like are housed in ceramic packages 6. The electrodes of the elements are connected by thin wires 7 to bonding pads 8 provided in the packages 6. The pads 8 are connected through electroconductive layers 9 to terminal pads 10, 10' provided on both the obverse and reverse sides of the packages. A seal-up lid 6' is fitted on the open end of each package. Separate semiconductor memories 5 are thus manufactured. These memories are stacked by using solder 4. The lowest memory 5 is attached by solder 4' to a terminal board 11 which has external leads 2, carrier pads 13 and electroconductive layers 14 so that a stack-structured device is provided. According to this constitution, assembly is simplified and cost is reduced.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7371879A JPS55165661A (en) | 1979-06-12 | 1979-06-12 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7371879A JPS55165661A (en) | 1979-06-12 | 1979-06-12 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55165661A true JPS55165661A (en) | 1980-12-24 |
JPS614189B2 JPS614189B2 (en) | 1986-02-07 |
Family
ID=13526275
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7371879A Granted JPS55165661A (en) | 1979-06-12 | 1979-06-12 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55165661A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59136963A (en) * | 1983-01-25 | 1984-08-06 | Sanyo Electric Co Ltd | Multilayer mounting structure of memory storage |
JPH0613540A (en) * | 1991-12-03 | 1994-01-21 | Nec Corp | Multichip module |
US5299092A (en) * | 1991-05-23 | 1994-03-29 | Hitachi, Ltd. | Plastic sealed type semiconductor apparatus |
US5381039A (en) * | 1993-02-01 | 1995-01-10 | Motorola, Inc. | Hermetic semiconductor device having jumper leads |
KR100238197B1 (en) * | 1992-12-15 | 2000-01-15 | 윤종용 | Semiconductor device |
KR100253325B1 (en) * | 1997-09-27 | 2000-04-15 | 김영환 | Land grid array package and fabricating method thereof |
-
1979
- 1979-06-12 JP JP7371879A patent/JPS55165661A/en active Granted
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59136963A (en) * | 1983-01-25 | 1984-08-06 | Sanyo Electric Co Ltd | Multilayer mounting structure of memory storage |
US5299092A (en) * | 1991-05-23 | 1994-03-29 | Hitachi, Ltd. | Plastic sealed type semiconductor apparatus |
JPH0613540A (en) * | 1991-12-03 | 1994-01-21 | Nec Corp | Multichip module |
KR100238197B1 (en) * | 1992-12-15 | 2000-01-15 | 윤종용 | Semiconductor device |
US5381039A (en) * | 1993-02-01 | 1995-01-10 | Motorola, Inc. | Hermetic semiconductor device having jumper leads |
KR100253325B1 (en) * | 1997-09-27 | 2000-04-15 | 김영환 | Land grid array package and fabricating method thereof |
Also Published As
Publication number | Publication date |
---|---|
JPS614189B2 (en) | 1986-02-07 |
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