JPS55157242A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS55157242A
JPS55157242A JP6596479A JP6596479A JPS55157242A JP S55157242 A JPS55157242 A JP S55157242A JP 6596479 A JP6596479 A JP 6596479A JP 6596479 A JP6596479 A JP 6596479A JP S55157242 A JPS55157242 A JP S55157242A
Authority
JP
Japan
Prior art keywords
film
type
forming
psg
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6596479A
Other languages
Japanese (ja)
Inventor
Izumi Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6596479A priority Critical patent/JPS55157242A/en
Publication of JPS55157242A publication Critical patent/JPS55157242A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent phosphorus from diffusing into a silicon substrate while heat treating a PSG film in a step of forming a surface stability protective film on the surface of a semiconductor element by forming a silicon nitride film on the surface of the element as ground for forming the PSG film. CONSTITUTION:There are formed a channel cutting p<+>-type 22, a field oxide film 23, a gate oxide film 24, a polysilicon gate electrode 25, an n-type source region 26, and an n-type drain region 27 on a p-type silicon substrate 21. Then, a photoresists film 28 is formed, and with the film 28 as a mask a connecting terminal forming portion 9 is formed to form a p-type high density layer 30. Thereafter, the photoresist film 28 is removed, a silicon oxide film 31 is formed on the entire surface, and a silicon nitride film 32 is then formed, and a PSG film 33 is formed thereon, and electrode connecting openings D, E, F and G are perforated thereat. After heat treating the film 33, the films 31, 32 of the openings D-G are removed, and an electrode 34 is formed.
JP6596479A 1979-05-28 1979-05-28 Manufacture of semiconductor device Pending JPS55157242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6596479A JPS55157242A (en) 1979-05-28 1979-05-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6596479A JPS55157242A (en) 1979-05-28 1979-05-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS55157242A true JPS55157242A (en) 1980-12-06

Family

ID=13302179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6596479A Pending JPS55157242A (en) 1979-05-28 1979-05-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55157242A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5972754A (en) * 1998-06-10 1999-10-26 Mosel Vitelic, Inc. Method for fabricating MOSFET having increased effective gate length

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52104087A (en) * 1976-02-27 1977-09-01 Hitachi Ltd Preparation of inter-layer insulation film utilized in multi-layer wir ing of electronic parts

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52104087A (en) * 1976-02-27 1977-09-01 Hitachi Ltd Preparation of inter-layer insulation film utilized in multi-layer wir ing of electronic parts

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5972754A (en) * 1998-06-10 1999-10-26 Mosel Vitelic, Inc. Method for fabricating MOSFET having increased effective gate length

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