JPS55154766A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS55154766A JPS55154766A JP6142479A JP6142479A JPS55154766A JP S55154766 A JPS55154766 A JP S55154766A JP 6142479 A JP6142479 A JP 6142479A JP 6142479 A JP6142479 A JP 6142479A JP S55154766 A JPS55154766 A JP S55154766A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- sio2 film
- field region
- polycrystalline
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 12
- 239000000758 substrate Substances 0.000 abstract 8
- 229910052681 coesite Inorganic materials 0.000 abstract 6
- 229910052906 cristobalite Inorganic materials 0.000 abstract 6
- 239000000377 silicon dioxide Substances 0.000 abstract 6
- 235000012239 silicon dioxide Nutrition 0.000 abstract 6
- 229910052682 stishovite Inorganic materials 0.000 abstract 6
- 229910052905 tridymite Inorganic materials 0.000 abstract 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 2
- 229910052782 aluminium Inorganic materials 0.000 abstract 2
- 230000002093 peripheral effect Effects 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
Abstract
PURPOSE:To eliminate disconnection of aluminum wire formed on a semiconductor substrate for a semiconductor device by reducing the thickness of the substrate at the peripheral edge becoming the field region of the substrate, burying it with laminate of a polycrystalline Si layer and an SiO2 film, and forming the entire surface substantially flat. CONSTITUTION:An SiO2 film 42 and an Si3N4 film 43 are sequentially laminated on an Si substrate 41, the field region at the peripheral edge is removed by a photoetching process, and the substrate 41 of this portion is also etched to reduce the thickness thereof. Then, a field SiO2 film 44 is coated from the side surface of the substrate 41 thus produced to the field region, polycrystalline Si layer 45 is grown on the entire surface, and an SiO2 film 46 is further laminated on the field region. In this manner, the surface of the substrate 41 is formed substantially flat, a thin gate SiO2 film 47 is formed on the element forming region, a polycrystalline Si gate electrode 47' is formed thereon, with the electrode 47' as a mask source and drain regios 49 and 50 are diffused and formed in the substrate 41, and aluminum wires 54 are mounted through an SiO2 film 51 on the regions 59 and 50.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6142479A JPS55154766A (en) | 1979-05-21 | 1979-05-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6142479A JPS55154766A (en) | 1979-05-21 | 1979-05-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS55154766A true JPS55154766A (en) | 1980-12-02 |
Family
ID=13170679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6142479A Pending JPS55154766A (en) | 1979-05-21 | 1979-05-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55154766A (en) |
-
1979
- 1979-05-21 JP JP6142479A patent/JPS55154766A/en active Pending
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