JPS55154647A - Multi-computer system by common memory - Google Patents

Multi-computer system by common memory

Info

Publication number
JPS55154647A
JPS55154647A JP6343279A JP6343279A JPS55154647A JP S55154647 A JPS55154647 A JP S55154647A JP 6343279 A JP6343279 A JP 6343279A JP 6343279 A JP6343279 A JP 6343279A JP S55154647 A JPS55154647 A JP S55154647A
Authority
JP
Japan
Prior art keywords
common memory
interruption
computer
computer system
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6343279A
Other languages
Japanese (ja)
Inventor
Susumu Ishikawa
Norio Shiki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6343279A priority Critical patent/JPS55154647A/en
Publication of JPS55154647A publication Critical patent/JPS55154647A/en
Pending legal-status Critical Current

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  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE: To increase the reliability of system, by providing the interruption producing circuit outputting an interruption generating signal and supplying the interruption producing signal to other computers, when one set of computer executes write-in or read-out of common memory.
CONSTITUTION: Two sets of computers 1a, 1b are connected to an interface mechanism 4 of a common memory 3 via interface sets 5a, 5b, and this mechanism 4 is connected to the common memory 3. Further, while one set of computer 1a or 1b executes the write-in or read-out of the common memory 3, an interruption generating signal is output from an interruption generating circuit 6 connected to the common memory 3, the interruption generating signal is fed to another computer 1b or 1a via interface mechanisms 7a, 7b, allowing to inform that the common memory 3 is during access.
COPYRIGHT: (C)1980,JPO&Japio
JP6343279A 1979-05-23 1979-05-23 Multi-computer system by common memory Pending JPS55154647A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6343279A JPS55154647A (en) 1979-05-23 1979-05-23 Multi-computer system by common memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6343279A JPS55154647A (en) 1979-05-23 1979-05-23 Multi-computer system by common memory

Publications (1)

Publication Number Publication Date
JPS55154647A true JPS55154647A (en) 1980-12-02

Family

ID=13229100

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6343279A Pending JPS55154647A (en) 1979-05-23 1979-05-23 Multi-computer system by common memory

Country Status (1)

Country Link
JP (1) JPS55154647A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62295112A (en) * 1986-06-14 1987-12-22 Mitsubishi Electric Corp Composite controller
JPS6478360A (en) * 1988-08-04 1989-03-23 Nec Corp Information processor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62295112A (en) * 1986-06-14 1987-12-22 Mitsubishi Electric Corp Composite controller
JPS6478360A (en) * 1988-08-04 1989-03-23 Nec Corp Information processor

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