JPS55145437A - Controlling system for logic circuit - Google Patents
Controlling system for logic circuitInfo
- Publication number
- JPS55145437A JPS55145437A JP5394979A JP5394979A JPS55145437A JP S55145437 A JPS55145437 A JP S55145437A JP 5394979 A JP5394979 A JP 5394979A JP 5394979 A JP5394979 A JP 5394979A JP S55145437 A JPS55145437 A JP S55145437A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- circuit
- signal
- output
- controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1731—Optimisation thereof
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To ensure the normal holding of the function for the controlled circuit, by forming the control circuit with the output of the dummy circuit and then securing the independent adaptation to the action change of the controlled signal for the control signal. CONSTITUTION:Output terminal TDD of the dummy circuit is connected to terminal TG1, and the timing signal is applied also to terminal TD1 at the time point same as application of the timing signal to terminal TGO. Thus the coincidence is secured at the front edges between the signals of terminals TGO and TD1, and accordingly the perfect coincidence is secured between the time point when the signal of terminal TD1 arrives and that when the output of the basic circuit is fixed. As a result, the output of the basic circuit can be extracted with no delay by applying the signal of terminal TDD to terminal TG1. In this way, the control circuit is formed with the output of the dummy circuit, and the independent adaptation is secured for the control signal to the action change of the controlled signal. Thus the function of the controlled circuit can be kept in the normal way.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5394979A JPS55145437A (en) | 1979-05-01 | 1979-05-01 | Controlling system for logic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5394979A JPS55145437A (en) | 1979-05-01 | 1979-05-01 | Controlling system for logic circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55145437A true JPS55145437A (en) | 1980-11-13 |
Family
ID=12956962
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5394979A Pending JPS55145437A (en) | 1979-05-01 | 1979-05-01 | Controlling system for logic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55145437A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01165212A (en) * | 1987-10-05 | 1989-06-29 | General Electric Co <Ge> | Impedance converting circuit for multibit parallel digital signal circuit |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5335464A (en) * | 1976-09-14 | 1978-04-01 | Nec Corp | Main and subordinate flip flop circuit |
JPS53139456A (en) * | 1977-05-11 | 1978-12-05 | Nec Corp | Clock driver circuit |
-
1979
- 1979-05-01 JP JP5394979A patent/JPS55145437A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5335464A (en) * | 1976-09-14 | 1978-04-01 | Nec Corp | Main and subordinate flip flop circuit |
JPS53139456A (en) * | 1977-05-11 | 1978-12-05 | Nec Corp | Clock driver circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01165212A (en) * | 1987-10-05 | 1989-06-29 | General Electric Co <Ge> | Impedance converting circuit for multibit parallel digital signal circuit |
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