JPS55143825A - Digital phase shifter - Google Patents

Digital phase shifter

Info

Publication number
JPS55143825A
JPS55143825A JP5123379A JP5123379A JPS55143825A JP S55143825 A JPS55143825 A JP S55143825A JP 5123379 A JP5123379 A JP 5123379A JP 5123379 A JP5123379 A JP 5123379A JP S55143825 A JPS55143825 A JP S55143825A
Authority
JP
Japan
Prior art keywords
switch
shift register
phase shift
constitution
shift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5123379A
Other languages
Japanese (ja)
Inventor
Yoshihiko Akaiwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5123379A priority Critical patent/JPS55143825A/en
Publication of JPS55143825A publication Critical patent/JPS55143825A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To increase the number of states of the phase shift quantity with a small number of constitution parts, by making repeat frequencies of clock pulses of shift registers, which are included in respective unit circuits which are cascaded, different from one another by integral multiples. CONSTITUTION:An input signal is applied from terminal 1 to two-state shift register 21, and outputs of respective stages are applied to switch 41, and one of them is selected by the signal applied to control signal terminal 5. The output of switch 41 is applied to next shift register 22, and one of outputs of respective stages is selected by switch 42. The two-stage shift register and the switch are combined to constitute a set of the unit circuit in this manner, and these unit circuits are cascaded. Clock pulse frequencies of shift registers are made different from one another by integral multiples, and they are 8 times, 4 times and twice as high as the input clock frequency respectively for eight kinds of state of phase shift. As a result, the number of states of the phase shift quantity can be increased with a small number of constitution parts.
JP5123379A 1979-04-25 1979-04-25 Digital phase shifter Pending JPS55143825A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5123379A JPS55143825A (en) 1979-04-25 1979-04-25 Digital phase shifter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5123379A JPS55143825A (en) 1979-04-25 1979-04-25 Digital phase shifter

Publications (1)

Publication Number Publication Date
JPS55143825A true JPS55143825A (en) 1980-11-10

Family

ID=12881219

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5123379A Pending JPS55143825A (en) 1979-04-25 1979-04-25 Digital phase shifter

Country Status (1)

Country Link
JP (1) JPS55143825A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58161414A (en) * 1982-03-18 1983-09-26 Fujitsu Ltd Digital signal variable delay circuit
EP0106499A2 (en) * 1982-09-16 1984-04-25 Ampex Corporation Shift register delay circuit
JPS6296879A (en) * 1985-10-24 1987-05-06 Nec Corp Timing control circuit
JPS62176344A (en) * 1986-01-30 1987-08-03 Nec Corp Timing phase correction circuit
EP3238064A4 (en) * 2014-12-25 2018-12-05 INTEL Corporation Method, apparatus, system for centering in a high-performance interconnect

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5428559A (en) * 1977-08-08 1979-03-03 Nec Corp Signal delay device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5428559A (en) * 1977-08-08 1979-03-03 Nec Corp Signal delay device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58161414A (en) * 1982-03-18 1983-09-26 Fujitsu Ltd Digital signal variable delay circuit
EP0106499A2 (en) * 1982-09-16 1984-04-25 Ampex Corporation Shift register delay circuit
JPS6296879A (en) * 1985-10-24 1987-05-06 Nec Corp Timing control circuit
JPS62176344A (en) * 1986-01-30 1987-08-03 Nec Corp Timing phase correction circuit
EP3238064A4 (en) * 2014-12-25 2018-12-05 INTEL Corporation Method, apparatus, system for centering in a high-performance interconnect
US10560081B2 (en) 2014-12-25 2020-02-11 Intel Corporation Method, apparatus, system for centering in a high performance interconnect

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