JPS55140959A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS55140959A
JPS55140959A JP4792779A JP4792779A JPS55140959A JP S55140959 A JPS55140959 A JP S55140959A JP 4792779 A JP4792779 A JP 4792779A JP 4792779 A JP4792779 A JP 4792779A JP S55140959 A JPS55140959 A JP S55140959A
Authority
JP
Japan
Prior art keywords
memory
address
information
selection
output state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4792779A
Other languages
Japanese (ja)
Inventor
Akio Shoda
Yoshiharu Iwamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4792779A priority Critical patent/JPS55140959A/en
Publication of JPS55140959A publication Critical patent/JPS55140959A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increase the flexibility of the memory system by including previously the information to select the memory into the access order to be given to the memory and then giving the access through selection of the memories featuring the different velocities and possessing the independent address space.
CONSTITUTION: Order register 1 consists of operation part 11 and address designation part 12; and the type of the order, the memory selection information and the memory address to receive access are stored into parts 11 and 12 each. Then the information of part 11 is decoded by decoder 2, and the fixed output state is secured for FF3 based on the memory selection information. At the same time, memory control sequencer 10 is started. On the other hand, the address given from address designation part 12 is applied to selection circuit 7, and the input is selected for memory 20 or 30 which features the different velocities according to the output state of FF3 and also possesses the independent address space. Then the sending timing is decided by sequencer 10 for the data to memory 20 or 30 according to the output state of FF3. And the data output of memory 20 or 30 is selected by selection circuit 9 at the reading time.
COPYRIGHT: (C)1980,JPO&Japio
JP4792779A 1979-04-20 1979-04-20 Memory control system Pending JPS55140959A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4792779A JPS55140959A (en) 1979-04-20 1979-04-20 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4792779A JPS55140959A (en) 1979-04-20 1979-04-20 Memory control system

Publications (1)

Publication Number Publication Date
JPS55140959A true JPS55140959A (en) 1980-11-04

Family

ID=12788994

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4792779A Pending JPS55140959A (en) 1979-04-20 1979-04-20 Memory control system

Country Status (1)

Country Link
JP (1) JPS55140959A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0390348U (en) * 1989-12-26 1991-09-13

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5210737B2 (en) * 1973-03-02 1977-03-25
JPS52149037A (en) * 1976-06-04 1977-12-10 Hitachi Ltd Control circuit of memory containing plural kinds of memory element
JPS5376632A (en) * 1976-12-17 1978-07-07 Nec Corp Timing signal supply system of memory unit
JPS5429530A (en) * 1977-08-10 1979-03-05 Oki Electric Ind Co Ltd Memory control system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5210737B2 (en) * 1973-03-02 1977-03-25
JPS52149037A (en) * 1976-06-04 1977-12-10 Hitachi Ltd Control circuit of memory containing plural kinds of memory element
JPS5376632A (en) * 1976-12-17 1978-07-07 Nec Corp Timing signal supply system of memory unit
JPS5429530A (en) * 1977-08-10 1979-03-05 Oki Electric Ind Co Ltd Memory control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0390348U (en) * 1989-12-26 1991-09-13
JP2526047Y2 (en) * 1989-12-26 1997-02-12 横河電機株式会社 Bus slave device

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