JPS5513986A - Ic mounting structure - Google Patents

Ic mounting structure

Info

Publication number
JPS5513986A
JPS5513986A JP8759678A JP8759678A JPS5513986A JP S5513986 A JPS5513986 A JP S5513986A JP 8759678 A JP8759678 A JP 8759678A JP 8759678 A JP8759678 A JP 8759678A JP S5513986 A JPS5513986 A JP S5513986A
Authority
JP
Japan
Prior art keywords
bump
regist
soldering
chip
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8759678A
Other languages
Japanese (ja)
Other versions
JPS6041855B2 (en
Inventor
Hiroyuki Mabuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP53087596A priority Critical patent/JPS6041855B2/en
Publication of JPS5513986A publication Critical patent/JPS5513986A/en
Publication of JPS6041855B2 publication Critical patent/JPS6041855B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

PURPOSE:To mount the flip chip IC in smaller size by dividing the soldering bump into two parts on the IC chip and the circuit pattern and holding the latter bump with the soldering regist on the circuit pattern. CONSTITUTION:A soldering bump 12 is formed on a IC chip 11 through a plating or evaporating. A photosensitive regist 16 is laminated on a circuit substrate 15. Fine hole is provided through the regist at the position corresponding to the soldering bump 12 for a circuit pattern 14 by use of photographical process and then filled with a soldering bump 13. Bonding is effected by hot-melting the bumps 12 and 13. Since the bump 13 is held by the thick regist 16 at its circumference, the chip 11 is kept to be sufficcently high above the pattern 14 after hot-melting. Also, the bump 12 is formed to be so thin that there is no occurred a short circuit between the bumps. This enalbes to shorten the distance between the bumps significantly and thus to make the multi-pin type IC smaller in size.
JP53087596A 1978-07-18 1978-07-18 IC mounting structure Expired JPS6041855B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53087596A JPS6041855B2 (en) 1978-07-18 1978-07-18 IC mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53087596A JPS6041855B2 (en) 1978-07-18 1978-07-18 IC mounting structure

Publications (2)

Publication Number Publication Date
JPS5513986A true JPS5513986A (en) 1980-01-31
JPS6041855B2 JPS6041855B2 (en) 1985-09-19

Family

ID=13919369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53087596A Expired JPS6041855B2 (en) 1978-07-18 1978-07-18 IC mounting structure

Country Status (1)

Country Link
JP (1) JPS6041855B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58209194A (en) * 1982-05-31 1983-12-06 日本電気株式会社 Method of connecting via solder leadless chip carrier to printed circuit board
US6207550B1 (en) 1997-07-02 2001-03-27 Matsushita Electric Industrial Co., Ltd. Method for fabricating bump electrodes with a leveling step for uniform heights

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5940260B2 (en) * 2011-08-08 2016-06-29 株式会社カネカ New flexible printed circuit board with integrated conductive layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58209194A (en) * 1982-05-31 1983-12-06 日本電気株式会社 Method of connecting via solder leadless chip carrier to printed circuit board
US6207550B1 (en) 1997-07-02 2001-03-27 Matsushita Electric Industrial Co., Ltd. Method for fabricating bump electrodes with a leveling step for uniform heights

Also Published As

Publication number Publication date
JPS6041855B2 (en) 1985-09-19

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