JPS55118635A - Method of forming pattern - Google Patents

Method of forming pattern

Info

Publication number
JPS55118635A
JPS55118635A JP2562579A JP2562579A JPS55118635A JP S55118635 A JPS55118635 A JP S55118635A JP 2562579 A JP2562579 A JP 2562579A JP 2562579 A JP2562579 A JP 2562579A JP S55118635 A JPS55118635 A JP S55118635A
Authority
JP
Japan
Prior art keywords
layer
etching
mask
substrate
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2562579A
Other languages
Japanese (ja)
Inventor
Hidefumi Mori
Tatsuo Izawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP2562579A priority Critical patent/JPS55118635A/en
Publication of JPS55118635A publication Critical patent/JPS55118635A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Optical Integrated Circuits (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To provide a precise etching pattern on a semiconductor substrate by adopting an etching mask having a double structure in which mask layers of different etching speed are superimposed when forming the pattern by a dry etching process on the substrate. CONSTITUTION:The first layer 2 composed of a material having slower etching speed by an ion or sputter etching process than a substrate 1 such as, for example, Ti, Zr or Ta or the like on the substrate 1, and the second layer 3 composed of a material having faster etching speed by an ion etching process than a resist layer 4 and slower speed by a plasma etching process than the first layer 1 such as, for example, Au, Ag, Cu or the like on the second layer 2. When using such a mask, the respective layers are sequentially etched according to the pattern of the resist to function as a mask. Accordingly, it can reduce the thickness of the resist layer and prevent the diffraction effect when exposing the resist layer.
JP2562579A 1979-03-07 1979-03-07 Method of forming pattern Pending JPS55118635A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2562579A JPS55118635A (en) 1979-03-07 1979-03-07 Method of forming pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2562579A JPS55118635A (en) 1979-03-07 1979-03-07 Method of forming pattern

Publications (1)

Publication Number Publication Date
JPS55118635A true JPS55118635A (en) 1980-09-11

Family

ID=12171048

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2562579A Pending JPS55118635A (en) 1979-03-07 1979-03-07 Method of forming pattern

Country Status (1)

Country Link
JP (1) JPS55118635A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6057935A (en) * 1983-09-09 1985-04-03 Nec Corp Formation of fine pattern
JP2008063155A (en) * 2006-09-04 2008-03-21 Sumitomo Electric Ind Ltd Method for manufacturing diamond structure and diamond structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3975252A (en) * 1975-03-14 1976-08-17 Bell Telephone Laboratories, Incorporated High-resolution sputter etching

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3975252A (en) * 1975-03-14 1976-08-17 Bell Telephone Laboratories, Incorporated High-resolution sputter etching

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6057935A (en) * 1983-09-09 1985-04-03 Nec Corp Formation of fine pattern
JP2008063155A (en) * 2006-09-04 2008-03-21 Sumitomo Electric Ind Ltd Method for manufacturing diamond structure and diamond structure

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