JPS55110332A - Data collector - Google Patents

Data collector

Info

Publication number
JPS55110332A
JPS55110332A JP1813479A JP1813479A JPS55110332A JP S55110332 A JPS55110332 A JP S55110332A JP 1813479 A JP1813479 A JP 1813479A JP 1813479 A JP1813479 A JP 1813479A JP S55110332 A JPS55110332 A JP S55110332A
Authority
JP
Japan
Prior art keywords
data
hcpu
flp
detection
interruption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1813479A
Other languages
Japanese (ja)
Inventor
Shunji Matsuo
Hitoshi Kobayashi
Junji Miyazaki
Nobuyuki Kawanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1813479A priority Critical patent/JPS55110332A/en
Publication of JPS55110332A publication Critical patent/JPS55110332A/en
Pending legal-status Critical Current

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  • Investigating Or Analysing Biological Materials (AREA)

Abstract

PURPOSE: To make it possible to prevent absence of data when a center unit circuit is disconnected by providing an auxiliary memory medium between the center unit and sensor and then by buffering data there temporarily.
CONSTITUTION: At the point in time when data to be sent out to a center HCPU side are set up on floppy FLP, data collection terminal DC transfer a data transmission request signal to HCPU. Here, HCPU never accepts an interruption while a process higher in priority thaan DC is under way and accepts it at the point in time of the process end to send back an interruption acceptance signal showing a permit to send. Then, DC is put into a pending state until the above-mentioned signal is received and during this period, data from sensor controller SC are stored in FLP. Once an interruption acceptance signal is received by DC, DC reads from FLP data as much as one detection body PT and then transfers them to HCPU. Similarly, an interruption is sent from DC to HCPU, detection-body data by detection-body data, until no detection-body data resides in FLP.
COPYRIGHT: (C)1980,JPO&Japio
JP1813479A 1979-02-19 1979-02-19 Data collector Pending JPS55110332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1813479A JPS55110332A (en) 1979-02-19 1979-02-19 Data collector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1813479A JPS55110332A (en) 1979-02-19 1979-02-19 Data collector

Publications (1)

Publication Number Publication Date
JPS55110332A true JPS55110332A (en) 1980-08-25

Family

ID=11963124

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1813479A Pending JPS55110332A (en) 1979-02-19 1979-02-19 Data collector

Country Status (1)

Country Link
JP (1) JPS55110332A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3641502A (en) * 1969-04-18 1972-02-08 Int Computers Ltd Data recording apparatus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3641502A (en) * 1969-04-18 1972-02-08 Int Computers Ltd Data recording apparatus

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