JPS55103662A - Data processing unit - Google Patents

Data processing unit

Info

Publication number
JPS55103662A
JPS55103662A JP1014979A JP1014979A JPS55103662A JP S55103662 A JPS55103662 A JP S55103662A JP 1014979 A JP1014979 A JP 1014979A JP 1014979 A JP1014979 A JP 1014979A JP S55103662 A JPS55103662 A JP S55103662A
Authority
JP
Japan
Prior art keywords
data
cpu
buffers
memory
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1014979A
Other languages
Japanese (ja)
Inventor
Junichi Iwasaki
Toshinori Otsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1014979A priority Critical patent/JPS55103662A/en
Publication of JPS55103662A publication Critical patent/JPS55103662A/en
Pending legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE: To transfer data effectively with a simple constitution by controlling operation and non-operation of plural buffers by the control signal from a detection circuit and by forming a CPU and buffers on the same chip.
CONSTITUTION: A CPU, a program memory and a data memory are incorporated on the chip at least, and a memory extendable one-chip microcomputer is provided in the external. Here, tri-state address buffer i, data read controlling buffer k, data write controlling buffer l, two-way buffer j for data transfer, and circuit h which detects data transfer between the CPU and the external memory, etc., are provided. Then, by the control signal from circuit h, operating and non-operating of buffers are controlled to form the CPU and buffers on the same chip. Thus, data can be transferred effectively with a simple constitution.
COPYRIGHT: (C)1980,JPO&Japio
JP1014979A 1979-01-31 1979-01-31 Data processing unit Pending JPS55103662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1014979A JPS55103662A (en) 1979-01-31 1979-01-31 Data processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1014979A JPS55103662A (en) 1979-01-31 1979-01-31 Data processing unit

Publications (1)

Publication Number Publication Date
JPS55103662A true JPS55103662A (en) 1980-08-08

Family

ID=11742212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1014979A Pending JPS55103662A (en) 1979-01-31 1979-01-31 Data processing unit

Country Status (1)

Country Link
JP (1) JPS55103662A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57121751A (en) * 1981-01-20 1982-07-29 Matsushita Electric Ind Co Ltd Microprocessor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5326632A (en) * 1976-08-25 1978-03-11 Hitachi Ltd Common memory control unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5326632A (en) * 1976-08-25 1978-03-11 Hitachi Ltd Common memory control unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57121751A (en) * 1981-01-20 1982-07-29 Matsushita Electric Ind Co Ltd Microprocessor

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