JPS54976A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS54976A
JPS54976A JP6576277A JP6576277A JPS54976A JP S54976 A JPS54976 A JP S54976A JP 6576277 A JP6576277 A JP 6576277A JP 6576277 A JP6576277 A JP 6576277A JP S54976 A JPS54976 A JP S54976A
Authority
JP
Japan
Prior art keywords
semiconductor device
gold
silver
bonded
increasing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6576277A
Other languages
Japanese (ja)
Inventor
Hisao Katsuto
Hiroshi Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6576277A priority Critical patent/JPS54976A/en
Publication of JPS54976A publication Critical patent/JPS54976A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE: To remarkably reduce the thermal resistance, by increasing the microscopic contact area when a semiconductor substrate is bonded on a substrate holding metal through the use of composite plating layer of silver and gold.
COPYRIGHT: (C)1979,JPO&Japio
JP6576277A 1977-06-06 1977-06-06 Semiconductor device Pending JPS54976A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6576277A JPS54976A (en) 1977-06-06 1977-06-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6576277A JPS54976A (en) 1977-06-06 1977-06-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS54976A true JPS54976A (en) 1979-01-06

Family

ID=13296352

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6576277A Pending JPS54976A (en) 1977-06-06 1977-06-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS54976A (en)

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