JPS548988A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS548988A
JPS548988A JP7467177A JP7467177A JPS548988A JP S548988 A JPS548988 A JP S548988A JP 7467177 A JP7467177 A JP 7467177A JP 7467177 A JP7467177 A JP 7467177A JP S548988 A JPS548988 A JP S548988A
Authority
JP
Japan
Prior art keywords
semiconductor device
electrode
famos
al2o3
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7467177A
Other languages
Japanese (ja)
Inventor
Kazunari Shirai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7467177A priority Critical patent/JPS548988A/en
Publication of JPS548988A publication Critical patent/JPS548988A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881Programmable transistors with only two possible levels of programmation
    • H01L29/7884Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7886Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To make it possible to erase written information easily, by using a film of Si3 N4, Al2O3, etc., whose band gap against poly-crystal Si constituting an electrode is smaller than that of SiO2 as an insulating film separating the 1st gate electrode from the 2nd one for a FAMOS element in the double-gate structure.
JP7467177A 1977-06-23 1977-06-23 Semiconductor device Pending JPS548988A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7467177A JPS548988A (en) 1977-06-23 1977-06-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7467177A JPS548988A (en) 1977-06-23 1977-06-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS548988A true JPS548988A (en) 1979-01-23

Family

ID=13553917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7467177A Pending JPS548988A (en) 1977-06-23 1977-06-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS548988A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5079603A (en) * 1986-05-26 1992-01-07 Hitachi, Ltd. Semiconductor memory device
US5189497A (en) * 1986-05-26 1993-02-23 Hitachi, Ltd. Semiconductor memory device
US5904518A (en) * 1988-11-09 1999-05-18 Hitachi, Ltd. Method of manufacturing a semiconductor IC device having single transistor type nonvolatile memory cells

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5079603A (en) * 1986-05-26 1992-01-07 Hitachi, Ltd. Semiconductor memory device
US5189497A (en) * 1986-05-26 1993-02-23 Hitachi, Ltd. Semiconductor memory device
US5904518A (en) * 1988-11-09 1999-05-18 Hitachi, Ltd. Method of manufacturing a semiconductor IC device having single transistor type nonvolatile memory cells
US6255690B1 (en) 1988-11-09 2001-07-03 Hitachi, Ltd. Non-volatile semiconductor memory device
US6451643B2 (en) 1988-11-09 2002-09-17 Hitachi, Ltd. Method of manufacturing a semiconductor device having non-volatile memory cell portion with single transistor type memory cells and peripheral portion with MISFETs
US6777282B2 (en) 1988-11-09 2004-08-17 Renesas Technology Corp. Method of manufacturing a semiconductor memory device having a memory cell portion including MISFETs with a floating gate and a peripheral circuit portion with MISFETs
US6960501B2 (en) 1988-11-09 2005-11-01 Renesas Technology Corp. Method of manufacturing a semiconductor memory device having a non-volatile memory cell portion with single misfet transistor type memory cells and a peripheral circuit portion with misfets
US7071050B2 (en) 1988-11-09 2006-07-04 Hitachi, Ltd. Semiconductor integrated circuit device having single-element type non-volatile memory elements
US7399667B2 (en) 1988-11-09 2008-07-15 Renesas Technology Corp. Method of manufacturing a semiconductor integrated circuit device having single-element type non-volatile memory elements

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