JPS5486255A - Pll synthesizer - Google Patents

Pll synthesizer

Info

Publication number
JPS5486255A
JPS5486255A JP15293277A JP15293277A JPS5486255A JP S5486255 A JPS5486255 A JP S5486255A JP 15293277 A JP15293277 A JP 15293277A JP 15293277 A JP15293277 A JP 15293277A JP S5486255 A JPS5486255 A JP S5486255A
Authority
JP
Japan
Prior art keywords
pll synthesizer
gate
pulse
1khz
entrance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15293277A
Other languages
Japanese (ja)
Inventor
Toshio Tanizoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15293277A priority Critical patent/JPS5486255A/en
Priority to DE19782855122 priority patent/DE2855122A1/en
Publication of JPS5486255A publication Critical patent/JPS5486255A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE: To obtain a PLL synthesizer which enables accurate offset and a fine adjustment of every 1KHz by arranging a pulse swallow gate at the entrance of a programmable counter and by eliminating the oscillation pulses of a VCO as many times as the gate is preset at every pulse period of a reference frequency generator.
CONSTITUTION: At the entrance of programmable counter 4, pulse swallow NAND gate 7 is arranged and oscillation pulses of voltage control oscillator VCO6 are eliminated as many times as it is preset at every pulse period of reference frequency generator 1, so that a PLL synthesizer can be obtained which enables the accurate offset and a fine adjustment of every 1KHz.
COPYRIGHT: (C)1979,JPO&Japio
JP15293277A 1977-12-21 1977-12-21 Pll synthesizer Pending JPS5486255A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP15293277A JPS5486255A (en) 1977-12-21 1977-12-21 Pll synthesizer
DE19782855122 DE2855122A1 (en) 1977-12-21 1978-12-20 Normal frequency generator with phase control circuit - has pulse absorbing gate mounted between VCO and programmed counter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15293277A JPS5486255A (en) 1977-12-21 1977-12-21 Pll synthesizer

Publications (1)

Publication Number Publication Date
JPS5486255A true JPS5486255A (en) 1979-07-09

Family

ID=15551282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15293277A Pending JPS5486255A (en) 1977-12-21 1977-12-21 Pll synthesizer

Country Status (2)

Country Link
JP (1) JPS5486255A (en)
DE (1) DE2855122A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995020269A1 (en) * 1994-01-24 1995-07-27 BALDWIN, Douglas, R. Adjustable frequency synthesizer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5160148A (en) * 1974-09-26 1976-05-25 Hewlett Packard Yokogawa

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5160148A (en) * 1974-09-26 1976-05-25 Hewlett Packard Yokogawa

Also Published As

Publication number Publication date
DE2855122A1 (en) 1979-06-28

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