JPS5482142A - Information error detecting system - Google Patents

Information error detecting system

Info

Publication number
JPS5482142A
JPS5482142A JP15012777A JP15012777A JPS5482142A JP S5482142 A JPS5482142 A JP S5482142A JP 15012777 A JP15012777 A JP 15012777A JP 15012777 A JP15012777 A JP 15012777A JP S5482142 A JPS5482142 A JP S5482142A
Authority
JP
Japan
Prior art keywords
information
circuit
parallel
series
checked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15012777A
Other languages
Japanese (ja)
Inventor
Toshihiko Matsuda
Kazuya Hori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15012777A priority Critical patent/JPS5482142A/en
Publication of JPS5482142A publication Critical patent/JPS5482142A/en
Pending legal-status Critical Current

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  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To increase the reliability for the transfer information with the control mechanism requiring the series-parallel conversion function by comparing the contents per word between the decision circuit of the parallel information and the FF which supplies the series-parallel conversion information and then detecting the information error.
CONSTITUTION: The parallel information transfeered from the higherdevice is stored once in data buffer 1 to be checked through parity circuit 2 concurrently. The checked parallel information is converted to series information through control circuit 3. In case the lower device is the floppy disc, the clock bit is inserted and then transmitted to the lower device in the form of series data C. At the same time, signal C is supplied to FF9 via OR gate 8, and the contents of FF9 is compared with the parity bit of the parallel information at comparator circuit 10 per word. And if no coincidence is obtained, it means that the transfer error of the information takes place at circuit 3. And output signal f of circuit 10 features logic "1".
COPYRIGHT: (C)1979,JPO&Japio
JP15012777A 1977-12-14 1977-12-14 Information error detecting system Pending JPS5482142A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15012777A JPS5482142A (en) 1977-12-14 1977-12-14 Information error detecting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15012777A JPS5482142A (en) 1977-12-14 1977-12-14 Information error detecting system

Publications (1)

Publication Number Publication Date
JPS5482142A true JPS5482142A (en) 1979-06-30

Family

ID=15490064

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15012777A Pending JPS5482142A (en) 1977-12-14 1977-12-14 Information error detecting system

Country Status (1)

Country Link
JP (1) JPS5482142A (en)

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