JPS5481078A - Test method for wafer using wafer carrier - Google Patents

Test method for wafer using wafer carrier

Info

Publication number
JPS5481078A
JPS5481078A JP14903177A JP14903177A JPS5481078A JP S5481078 A JPS5481078 A JP S5481078A JP 14903177 A JP14903177 A JP 14903177A JP 14903177 A JP14903177 A JP 14903177A JP S5481078 A JPS5481078 A JP S5481078A
Authority
JP
Japan
Prior art keywords
wafer
integrated circuit
circuit chip
test
test method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14903177A
Other languages
Japanese (ja)
Inventor
Koji Hashiguchi
Yoshiaki Michiguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14903177A priority Critical patent/JPS5481078A/en
Publication of JPS5481078A publication Critical patent/JPS5481078A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE: To secure execution of the wafer level test without using the wafer prober by connecting plural number of conductive pins to be connected to the pad formed on the wafer to the test device.
CONSTITUTION: The pairs of proper voltage or current are applied to integrated circuit chip 4a, 4b, 4c or 4d on the wafer via conductive pin 12. And the expected value is compared with the output. Then the switch circuit within wiring region 3 is controlled by the external control signal after the test of one integrated circuit chip in order to select the next integrated circuit chip to be tested.
COPYRIGHT: (C)1979,JPO&Japio
JP14903177A 1977-12-12 1977-12-12 Test method for wafer using wafer carrier Pending JPS5481078A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14903177A JPS5481078A (en) 1977-12-12 1977-12-12 Test method for wafer using wafer carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14903177A JPS5481078A (en) 1977-12-12 1977-12-12 Test method for wafer using wafer carrier

Publications (1)

Publication Number Publication Date
JPS5481078A true JPS5481078A (en) 1979-06-28

Family

ID=15466146

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14903177A Pending JPS5481078A (en) 1977-12-12 1977-12-12 Test method for wafer using wafer carrier

Country Status (1)

Country Link
JP (1) JPS5481078A (en)

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