JPS5472925A - File memory system - Google Patents

File memory system

Info

Publication number
JPS5472925A
JPS5472925A JP14101377A JP14101377A JPS5472925A JP S5472925 A JPS5472925 A JP S5472925A JP 14101377 A JP14101377 A JP 14101377A JP 14101377 A JP14101377 A JP 14101377A JP S5472925 A JPS5472925 A JP S5472925A
Authority
JP
Japan
Prior art keywords
controllers
read request
write
controller
file memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14101377A
Other languages
Japanese (ja)
Inventor
Sadanobu Takashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14101377A priority Critical patent/JPS5472925A/en
Publication of JPS5472925A publication Critical patent/JPS5472925A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To shorten a processing time, by enabling a file memory unit, which can be connected to a plural number of controllers, to answer write and read request signals from each controller by being equipped with protective switches corresponding to controllers.
CONSTITUTION: Controllers 21 and 22 are provided which generate either data- write or read request signal answering command signals from electronic-computer organizations 31 and 32, and then, file memory unit 10 is provided to controllers 21 and 22 in common. This unit 10 is equipped with state control part 11, operation panel 12 and memory part 13, protective switches 40 and 50 are provided to panel 12 corresponding to controllers 21 and 22, and state control parts 11 is provided with write inhibit FFs 41 and 51, reservation state FF42, in-use display FFs 45 and 46, and the logic gate circuit. Then, it is made possible to answer a read request from either controller 21 or 22 while outputting a permit signal answering a write or read request signal from the other controller.
COPYRIGHT: (C)1979,JPO&Japio
JP14101377A 1977-11-22 1977-11-22 File memory system Pending JPS5472925A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14101377A JPS5472925A (en) 1977-11-22 1977-11-22 File memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14101377A JPS5472925A (en) 1977-11-22 1977-11-22 File memory system

Publications (1)

Publication Number Publication Date
JPS5472925A true JPS5472925A (en) 1979-06-11

Family

ID=15282155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14101377A Pending JPS5472925A (en) 1977-11-22 1977-11-22 File memory system

Country Status (1)

Country Link
JP (1) JPS5472925A (en)

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